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Need help with Digital/Analog Ground plane protel/altium

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difflvl

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I have attached the Altium Designer PCB. I think you need 6.3 and up to open it.

The board is contains a 56k dial up modem chipset. The left part, is the digital part, the right side, is the telephone line side device (analog part).

The board is 4 layers. I have the ground plane seperated into 2 planes, one is for digital and one for analog. I tie the digital and analog together under the analog IC.

I also have digital and analog ground copper pour on the top and bottom. Is this bad or necessary? What is the point of the copper pour anyway, assuming you have inner planes?

Is the spacing between the digital and analog ground planes proper or not large enough?

I got this PCB made, and I seem to be having some problems, so Im thinking maybe I have a problem with the digital/analog grounds and pours. The speaker output sounds distorted and its doesn't seem to be stable.

Do you see anything wrong with it?

Thanks
 

I have had a quick look at the but Now I'm not sure if this is corrrect but in my case I have found 5 error when I run the DRC rule check

here they are


You need to check them your end but it's what I'm getting and this could be your problem ????

wizpic
Code: 
Summary
Warnings Count 
Via(s)/Pad(s) touching plane splitting primitives on following planes 1 
Total 1 

Rule Violations Count 
Short-Circuit Constraint (Allowed=No) (All),(All) 2 
Broken-Net Constraint ( (All) ) 1 
Clearance Constraint (Gap=0.205mm) (All),(All) 2 
Width Constraint (Min=0.1mm) (Max=0.5mm) (Preferred=0.205mm) (All) 0 
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0 
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 0 
Room main (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('main')) 0 
Width Constraint (Min=0.205mm) (Max=0.5mm) (Preferred=0.45mm) ((InNet('RING') OR InNet('Tip'))) 0 
Clearance Constraint (Gap=0.45mm) ((InNet('RING') OR InNet('Tip'))),(All) 0 
Clearance Constraint (Gap=0.254mm) ((InNet('BRIDGE_CC') OR InNet('Ring2') OR InNet('Ring3') OR InNet('Tip2') OR InNet('Tip3'))),(All) 0 
Width Constraint (Min=0.205mm) (Max=0.5mm) (Preferred=0.305mm) ((InNet('BRIDGE_CC') OR InNet('Ring2') OR InNet('Ring3') OR InNet('Tip2') OR InNet('Tip3'))) 0 
Minimum Annular Ring (Minimum=0.205mm) (All) 0 
Total 5 


--------------------------------------------------------------------------------

Warnings
Via(s)/Pad(s) touching plane splitting primitives on following planes 
Via (41.864mm,-10.747mm) Top Layer to Bottom Layer: InternalPlane1 
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--------------------------------------------------------------------------------
Short-Circuit Constraint (Allowed=No) (All),(All) 
Track (39.015mm,-14.522mm)(39.015mm,-12.522mm) Bottom Layer Pad A1-2(39.015mm,-14.522mm) Bottom Layer 
Track (39.015mm,-14.522mm)(39.015mm,-12.522mm) Bottom Layer Track (39.015mm,-15.621mm)(39.015mm,-14.522mm) Bottom Layer 
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Broken-Net Constraint ( (All) ) 
Net GND
 
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Clearance Constraint (Gap=0.205mm) (All),(All) 
Track (39.015mm,-14.522mm)(39.015mm,-12.522mm) Bottom Layer Pad A1-2(39.015mm,-14.522mm) Bottom Layer 
Track (39.015mm,-14.522mm)(39.015mm,-12.522mm) Bottom Layer Track (39.015mm,-15.621mm)(39.015mm,-14.522mm) Bottom Layer 
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    D

    difflvl

    Points: 2
    Helpful Answer Positive Rating
Redefine default rules.
Electrical _ Clearance from .127 mm to something like .2mm or 1 mm whatever suits you.
Reroute mentioned tracks and you are good to go.
But once you complete re-routing run a drc check again to find if there are any more errors.
 

Thanks.

Is the additional copper pour top/bottom bad if I already have an inner plane?
 

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