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Gated clock module for reducing power consumption

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oliver.nie

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Hi, All.

I decide to use gated clock to reduce power consumption.
Can anyone give me a good RTL modul for gated clock?
And is there anything to be concerned during simulation and synthesis?

Thanks.

Oliver Nie
 

oliver nie

hi

can u please eloberate as to tell wat exactly u r looking for ...

suresh
 

latch async icg cell

gated clock cell is a special cell for glitch should be treated as macro cell!!
 

icg cts clock

I divided my chip design into several modules and some modules will be stopped by disable its clock. I know clock tree consumes power very much.

And some papers say that it is slow for simulation on gated clock design. I am not very clear about this statement. Why slow? In addition, I use mentor's modelsim to do simulation.

Anyone here have the experience? Anything need to be taken care of on gated clock design? During simulation or Synthesis or P&R? I have no experience about it, even I don't know how to ask the questions.

Hope your advice.

Regards,

Oliver.Nie
 

gated clock domain

Hi ,


Gate clocks are to reduce dynamic power consumption .
Regrding care about clk gating

1) Are you sure when you should gate ex : you should not request any subsys when clk gating is active and no clk ?
2) Is your clk gating is to devide clk ? , then you should take care about phase of clk gating signal ?
3) On what even you want to on/off clk and how it will resume during this time your soc architecture should ensure no expectation from same module . if you have any interrupts do you want to resume ? if you have peripheral req do you need to resume clk or not in those cases is your detection of this resume logic should be async .....


In simple , clk gating is Architecture dependant ...


Thanks & Regards
yln
 
Re: about Gated clock

Hi, yln

Thanks a lot. Your suggestion is helpful. By now, I just want some module to be
stopped or resumed by gated clock which is controled by cpu register's setting.

And I find a typical gated clock module to do this work. See it in attachment.

Thanks again.

Oliver.Nie
 

Re: about Gated clock

Hi ,

I saw your implementation it is ok . But please take care of following points .

1) When do you want to latch data , if you see do you need to take data when clk_en high and clk is with pos edge ? then you need to balance delay for clk_en path and clk path .

Other wise there is a possibility of missing data for first clk cylce ...


Thanks & Regards
yln
 

Re: about Gated clock

Hi, Yln.

I think clk_en will be synchronous on clk postive edge. And I will pay attention to the fisrt cycle.

Thanks for your suggestion.

Best Regards,

Oliver.Nie
 

about Gated clock

gated clock design has some additional influence on:

1. STA, both pre-STA and post-STA, the clock wave form should not be clipped by the gate.

2. Design for Test flow, the gate control signal must be controllable in testing mode.

3. additional effort on clock tree generation, i have not hand-on experience about this.
 

Re: about Gated clock

material is reaaly good...
thanx for uploading such material
 

Re: about Gated clock

thanks for your answer.i think
i simulation we dont go for synthesis for gated clock.
 

Re: about Gated clock

gated clock, use like gck cell type



Added after 4 minutes:

one more
 

Re: about Gated clock

advanced timing
 

Re: about Gated clock

Here is a simple and reliable clock gating scheme. Only one gate and one latch and it will not fail.

 

Re: about Gated clock

pathmill user guide ,
 

about Gated clock

Actually you can have two types of clock gating.

1) Module level clk gating. Like the one describe by Oliver here. The clk is gated by config bit at the source, and gates the clk to complete module. This is manually instantiated gate.

2) leaf-level clk gating. This is done by tools like power compiler from synopsys. Based on logic cone, tool will infer the conditions under which the flop can be get a new data, and use it to gate the clk to the flop. This is done during synthesis and is coding style dependent.
 

Re: about Gated clock

In DFT you will gave to take care about the gated clocks so that the testability of the ciriuit is not complicated
 

Re: about Gated clock

rakko said:
Here is a simple and reliable clock gating scheme. Only one gate and one latch and it will not fail.

Click to expand...
better use a low level sensitive latch
 

Re: about Gated clock

For DFT reasons you'll want to allow the clock to propagate during test.
I also add resets and have two flavors. One to gate on the positive edge and one to gate on the negative edge.
 

about Gated clock

the synthesis tool can help u insert gated clk automatically if u do power constrains
 

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