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Supporting Partial-power-down

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yann_sun

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What does "partial-power-down" mean?
How to implement this "partial power-down"?
:arrow::arrow:
 

can you give little more explanation for the question?
 

Hi ,

If I understand correctly , This is one of the SOC methodolgy to shut down power to some of the hard macros like memories and you can shutdown power to functionality of subsys too .

partition of which domains need to be in separate power is depends on your architecture

ex: you can shut down power to onchip SRAM ( scratch pad) while processor is in standy ....

please let me know if you have specific queries ....


THanks & Regards
Yln
 

    yann_sun

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yln2k2 said:
Hi ,

If I understand correctly , This is one of the SOC methodolgy to shut down power to some of the hard macros like memories and you can shutdown power to functionality of subsys too .

partition of which domains need to be in separate power is depends on your architecture

ex: you can shut down power to onchip SRAM ( scratch pad) while processor is in standy ....

please let me know if you have specific queries ....


THanks & Regards
Yln

Yeah, you are quite right, it means shut down some of the subsystem of your chip or product which has no operation currently to reduce the power consumption.
 

    yann_sun

    Points: 2
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I met with this problem during the analyse of a bus-interface circuit. Thanks for your help, yln2k2 and beta0
 

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