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high impedance in vhdl

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btminzon

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vhdl high impedance

hi, i have a doubt using high impedance in vhdl:

I have two imputs, EAB01(0) and EAB01(1).

if (EAB01 = "01") then
reg <= data;
selec_toff <= "10";
elsif (EAB01 = "10") then
reg <= data;
selec_toff <= "01";
elsif (EAB01 = "11") then
reg_16 <= dados;
create_toff_16bit <= selec_toff;
elsif ((EAB01 = "00") or (EAB01 = "ZZ")) then
create_toff_16bit <= "00";
end if;

with selec_toff and create_toff_16bit been,

signal selec_toff: std_logic_vector(1 downto 0);
signal create_toff_16bit: std_logic_vector(1 downto 0);
EAB01: in std_logic_vector(1 downto 0);


but this assignment doesn´t work. How can i detect this high impedance? thank you
 

high impedance vhdl

There is no way to detect high impidance condition in the sintizable model of VHDL. Because when you have two or more devices interconnect there is always a leakage current or pull resistor (recommended).
Also in your code I would recomend to use case statement instead of if-elsif elsif construction..

Regards,
 

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    btminzon

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