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setup and holdtime violation

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pd_vlsi

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hello,

hw would one remove....setup and holdup violations....in an semicustom design...consider using Cadence SoC Encounter...

if buffers has to be added, resized...whats the difference betwn the buffers for setup and hold time removal.....

what r the other techniques....when the automated Timing optimization....cant fix all violations...


thanks
 

For setup time you need clock buffer to change clock skew. For hold time you need delay buffer to slow the data.
 
In encounter flow....though we do setup analysis before Clock synthesizing ....in that case hw we can change skew?

if we do ....setup analysis after clock tree....then that can be one of the solution....

correct me if i am wrong.....

thanks
 

hi
As laglead had said, you can fix ur setup and hold violators when u are P&Ring ur design.
and the conmon method is that you can decrease ur frequency if ur clock requirement is not very high.
Regards
sevid
 

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