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How to Divide Clock Frequency

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btminzon

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divide clock

Hi ,

I need to divide the clock frequency by 8. Any one have this code in vhdl, using Quartus? thanks a lot

Regards

Breno
 

divide clock frequency

A simple way to do this is use a counter.

library IEEE;
use IEEE. std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity Div_Frec is
port( CLK : in std_logic;
RST : in std_logic;
CLK_DIV : out std_logic);
end Div_Frec;

architecture Divide_Frec of Div_Frec is
signal Qp, Qn : std_logic_vector(2 downto 0);

begin
comb : process(Qp)
begin
Qn <= Qp+1;
CLK_DIV <=Qp(2);
end process comb;

sec : process(CLK,RST)
begin
if(RST = '1') then
Qp<="000";
elsif(CLK'event and CLK ='1') then
Qp <= Qn;
end if;
end process;
end Divide_Frec;
 

how to divide frequency

Use a simple binary 3-bit counter. Division of frequency by 2 is made with a T-type trigger.
 

how to divide clock

entity Ad_Clk_Div is
port(
Div_Fac : in unsigned(3 downto 0);-- Division Factor (put 8 here)
Clk : in std_logic; -- Global Clk
Reset : in std_logic; -- Global Reset
DClk : out std_logic -- Divided Clk Out
);
end entity Ad_Clk_Div;

architecture Ad_Clk_Div_Arch of Ad_Clk_Div is
signal count : unsigned(3 downto 0);
begin

process(Clk,Reset)

begin
if(Reset = '0')then
count <= (others => '0');
DClk <= '0';
elsif(RISING_EDGE(Clk))then
if(count = Div_Fac)then
count <= (others => '0');
DClk <= not DClk ;
else
count <= count + 1 ;
end if;
end if;

end process;
end architecture Ad_Clk_Div_Arch;
 

divide clock frequency in verilog

just flop the signal three times.

q1 <= d;
q2 <= q1;
q3 <= q2;

q3 will give u a divide by eight signal.
 

divide clock for count time

If you don't mater about skew, and need low power, the best is to use tree divideers by 2 y cascade.

For example:

process(clk_in,reset)
begin
if reset='1' then
clk_d2 <= '0';
elsif clk_in'event and clk_in='1' then
clk_d2 <= not clk_d2;
end if;
end process;

process(clk_d2,reset)
begin
if reset='1' then
clk_d4 <= '0';
elsif clk_d2'event and clk_d2='1' then
clk_d4 <= not clk_d4;
end if;
end process;

process(clk_d4,reset)
begin
if reset='1' then
clk_d8 <= '0';
elsif clk_d4'event and clk_d4='1' then
clk_d8 <= not clk_d8;
end if;
end process;

Better coding using 'generate'.
 

    B

    btminzon

    Points: 2
    Helpful Answer Positive Rating
divide clock by

Yes, I have problem with space in my Altera. I'm developing a Pulse generator, that receives a 16 bit in paralel and another 16 bits, after receiving the first one. This 2 groups os 16 bits contains the number of pulses to count, and the exit will be high until count first number, and exit will be low, untill count the second number. I'm using 61 macrocells of 64, using max 3064. And i also need speed. I have a clock of 8Mhz, and need to divide per 8, to achive 1us per clock cycle. I'll try all of them, and wich were the best "cost-benefict", i'll use it. Thanks every one!!!

Best Regards

Breno
 

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