Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Summation in verilog HDL---urgent

Status
Not open for further replies.
P

param

Member level 2
Joined
Sep 9, 2005
Messages
49
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,649
hi,
i have to find the summation of a sequence of data...
for example, i have
always @(posedge clk)
begin
if ( cntrl == 1'b0)
begin
reg1 = 16'b0000000000000000;
reg2 = 16'b0000000000000000;
product = 16'b0000000000000000;
end

else
product <= reg1 * reg2;
end
then let product = 11
22
33
.
.
.

now i how to find the summation of product!!!
like sum <= 11 + 22 + 33 + ...

In anticipation of ur help
regards
 

Store the result of the product in registers (memory) then add on a different clock cycle.
 

    P

    param

    Points: 2
    Helpful Answer Positive Rating
hi, see the answer in asic design methodologies. its an issue of using adders for the given implementation. based on the no. of bits input that input provides, find the maximum bits of output that will result if added and try the rtl implementation of that.
 

    P

    param

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top