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Deep submicron technology means,using transitoros of smaller size with faster switching rates. As we know from Moore's law the size of transistors are doubled by every year in a system,the technology has to fit those inc in transistors in small area with better performance and low-power.
Submircon Name is due to 0.35um>0.25um>0.18um>0.13um as reduced in sizes of micron level.
Several issues in Deep submicron technology are:
Challenges for Low-Power Design
Better Signal Integrity or Signal quality
High-Desity and Design Complexity
Packing such complex chips and Testing
Also Cost efffective approach to reduce Higher Design NRE
Of course deep-submicron even nano technology means high-density integration.
In my opion the biggest problem we should face in nano design are leakage, temperature susecibility, signal/power intergrity and device parameter variability.
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