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Programming ADS with Verilog-A

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mido_h14

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ADS with Verilog

I have Advanced Desing System 2004A (ADS2004A), and I want to write a Verilog-a component..
I found in its manual that I can do that by adding "VerilogA_Load component" from the "Devices-Verilog-A palette" ... But I can't find that palette in my 'A'DS version.. then, I have some questions:
1) According to the manual, can I write Verilog-A under Windows?
2) How can I add a verilog-a component and edit its code in ads?
3) I noticed that the manuals are mainly related to Linux platforms, isn't there any tutorial for verilog-a that's related to Window?

Thanks,
 

Re: @DS with Verilog

mido_h14 said:
I have Advanced Desing System 2004A (ADS2004A), and I want to write a Verilog-a component..
I found in its manual that I can do that by adding "VerilogA_Load component" from the "Devices-Verilog-A palette" ... But I can't find that palette in my 'A'DS version.. then, I have some questions:
1) According to the manual, can I write Verilog-A under Windows?
2) How can I add a verilog-a component and edit its code in @DS?
3) I noticed that the manuals are mainly related to Linux platforms, isn't there any tutorial for verilog-a that's related to Window?

Thanks,
Click to expand...

1) Yes, You can write Verilog-A on ads under windows.

2)To add a verylog-A loader in ADS, you've first to install the Verilog-A associated Design kit, to do that:
- In 'A'DS main window, open: Design Kit>Install Design Kit> .... then browse for the following:
Code: 
C:\ADS2004A\tiburon-da\ads\designkits\tiburon-da_veriloga

If you have 'A'DS installed on another location, change the above, be sure that other fields are automatically filled in BLACK colour (not RED that means errors)

then, hit OK..

Open a new schematic, you will be able to open the: Devices-VerilogA palette, choose Verilog-A Loader from it (at the end of it)

Till now, I didn't write a verilog code to any component in ads, I hope that someone else continue this part

3) Manuals already include Windows based tutorials (It doesn't differ between Windows and Unix..

Hope that helped :)
Salam,
Ahmad,
 

    M

    mido_h14

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Re: @DS with Verilog

ahmad_abdulghany said:
Till now, I didn't write a verilog code to any component in @DS, I hope that someone else continue this part
Click to expand...

Yes, please anybody tell how to add Verilog-A blocks in ads...

I'm sure that someone will do, and waiting for help from you

Thank you for help,
 

Re: ADS with Verilog

Ahmed_Sawaf said:
ahmad_abdulghany said:
Till now, I didn't write a verilog code to any component in @DS, I hope that someone else continue this part
Click to expand...

Yes, please anybody tell how to add Verilog-A blocks in ads...

I'm sure that someone will do, and waiting for help from you

Thank you for help,
Click to expand...

In another topic i have answered this part. It can be rather tedious task to go through the process of running a Verilog-A model in ADS for the first time or without much experience in ADS, which is why I wrote a tutorial and attached it to my other reply that is located here:



Ahmed's steps are correct and are essentially the starting point. After these you'd have to modify the AEL file to instantiate the model and attributes. For detailed step-by-step instructions visit the above link and download the pdf file.
 

Re: ADS with Verilog

kert said:
... I wrote a tutorial and attached it to my other reply that is located here:



Ahmed's steps are correct and are essentially the starting point. After these you'd have to modify the AEL file to instantiate the model and attributes. For detailed step-by-step instructions visit the above link and download the pdf file.
Click to expand...

The link seems to have changed over the time and now leads to somewhere else.

Here's the updated link: https://www.edaboard.com/threads/61497/#post758754
 

Re: ADS with Verilog

i tried with exact steps you have mentioned in the document
but i ended up with the following status/error message,
Warning detected by hpeesofsim during netlist flattening.
Instance `X1':
`b0' is not a valid parameter for an instance of `DCO'. Ignoring it.
Warning detected by hpeesofsim during netlist flattening.
Instance `X1':
`b1' is not a valid parameter for an instance of `DCO'. Ignoring it.
Warning detected by hpeesofsim during netlist flattening.
Instance `X1':
`b2' is not a valid parameter for an instance of `DCO'. Ignoring it.
Warning detected by hpeesofsim during netlist flattening.
Instance `X1':
`b3' is not a valid parameter for an instance of `DCO'. Ignoring it.
Warning detected by hpeesofsim in topology check during circuit set up.
Number of nodes with only one device attached (topology corrected): 1
Warning detected by hpeesofsim during DC analysis `Tran1'.
A virtual resistance of 1 pOhms
was added to branch SRC4.i.

with an empty window , instead of the result windows that you have shown in the document,

waiting for your reply



kert said:
The link seems to have changed over the time and now leads to somewhere else.

Here's the updated link: https://www.edaboard.com/threads/61497/#post758754
Click to expand...
 

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