Starting with CPLD and some question

Hi,

I'm going to start using CPLDs chips from Xilinx soon (with the XC2C32 and XC9536XL) and was digging for information about them for a while. Finally installed the WebPack software (the Linux version), get comfortable with it (syntesized one design too) but I'm still learning....

I have parraler programmer already and I'm just waiting for chips.

But to my goal - I plan to use CPLD as replacement for my cmos based logic circuits. Mostly for smaller PCB sizes and to simplify tracing as the CPLD's I/O pins can be locked manually.

I'd like to make CPLD interefere with more classical chips (cmos 4xxx series) still but it shouldn't be difficult especially that for I/O there is separate voltage supply.

But I have few question as I might need to buy some extra parts eventually in an advance:

- what is voltage tolerance for supply? The ColdrunnerII's specs say 2V MAX but what about using it with higher V anyway (2.4V for an example)? Will it fry instantaneously? (even at very low clocks?)

- will be V regulator like the 78L02 sufficient to power that CPLD?
(looking at its specs it should)

- Xilinx software allow to set many different timing constrains. As I could understand providing the clock isn't needed for plain asynchronous operation?

- I have universal PCB board with place for PLCC44 socket in it. I plan to make my own developing/experimenting board with CPLD. Any special advices for that?


Regards and thanks,

Radek

2.4V should be ok. These CPLDs are resilient parts. And they aren't that expensive so I would say just try it.

Asynchronous designs or modules do not need clocks.

gliss said:

2.4V should be ok. These CPLDs are resilient parts. And they aren't that expensive so I would say just try it.

Click to expand...

Silly of me... I can always put a diode for a drop of voltage with added plus of reverse voltage protection. Because I don't plan use CPLD with any higher clock the current flowing via diode should be minimal.

Asynchronous designs or modules do not need clocks.

Click to expand...

Well... I just didn't know if input clock is necessary for CPLD to function. But it isn't as it seems and this is excellent news.

I can not wait for my chips!

if you trying to impliment any storage functionality ie flip flop you must have a clock

Iouri said:

if you trying to impliment any storage functionality ie flip flop you must have a clock

Click to expand...

For some time I will be using CPLD mostly as replacement of my previous cmos 40xx series chips. There are usual logic gates only and it will be sufficient for my project. But later I will implement clocking for sure. Actually I'm even thinking about using some µC for that as it can act as clock source too.

But for now simple logic gates will be enough.

that's can be a problem in the old days we use to use RS flip flops or clock flip flop from any output, with CPLD/FPGA watch out all clocking must be done from the same source