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Urgent verilog question, please help.

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tiger_shark

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Hi!

In VHDL, you could use GENERIC and use for loop to instantiate variable number of modules, if need be. The synthesizer would then unfold the for loop and basically replicate the code as required.

My question is : Do we have the same approach for verilog? For instance, I have a submodule My_MODULE and I need to instantiate it X times where X is defined as PARAMETER (fixed). Then how would the naming for those generated modules would be?

Thank you very much
TS
 

I think in verilog to do this it's much simpler. For Verilog, you might want to try something like this:

Code: 
module higher_module           // define a module to instantiate the My_MODULE
parameter x = 10;              // declare a paramter x, set it to 10
input [x:0] a;                 // create input ports for My_MODULE
output [x:0] b;                // create output ports for My_MODULE
My_MODULE xmod[x:10] (b, a);   // create an array of 11 My_MODULES and connect ports
endmodule

Then to specify a single My_MODULE in the array you would do:
Code: 
xmod[x-1]
for the MSB and
Code: 
xmod[0]
for the LSB
Also, you can do slices or parts like this:
Code: 
xmod[6:4];
 
hi ... i feel u have done VHDL and now new in Verilog ... same as me ...

So first u need to find and clerify the major differences between these two ... for that i got that file ... sorry i am not having its link ...

it also guide for looping ...
 

Hi,

THanks for the advise. How if the input to the module My_MODULE is itself a vector a[N-1], b[M-1]? Then how would you define a, b?

Thanks
TS

Added after 25 minutes:

yet another question:

If the submodule MY_MODULE has a parameter, how can I use defparam to assign a value to all the instantiated MY_MODULE copies?

Thanks for the help,
TS



//---------------------------------------------------//
sample code that i am working with:

module adder_generic(a_in,b_in,c_out);
parameter NUM_OF_INST = 30;
parameter WIDTH =14;

input [NUM_OF_INST*WIDTH-1:0] a_in ;
input [NUM_OF_INST*WIDTH-1:0] b_in ;
output [NUM_OF_INST*WIDTH-1:0] c_out;
integer i;

for (i=0;i<NUM_OF_INST;i=i+1)
begin
defparam adder_inst.WIDTH = WIDTH;
end
adder adder_inst[NUM_OF_INST-1:0] (a_in,b_in,c_out);

endmodule
 

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