Questions referring to the ICs Lab

ic's questions

i ask in the ic's lab
1- why we use the pad oxide(please in detals)?
2- the oxide spacer behind the ply gate
3-what the latch up that the Epitaxy can decrease it?
4- what the joinedbetween the dry oxidation and the ?
5-what the plan of the silicon which the fabrication begain(100)or(111)?

Re: ic's questions

moustafa ali said:

i ask in the ic's lab
1- why we use the pad oxide(please in detals)?
2- the oxide spacer behind the ply gate
3-what the latch up that the Epitaxy can decrease it?
4- what the joinedbetween the dry oxidation and the ?
5-what the plan of the silicon which the fabrication begain(100)or(111)?

Click to expand...

Sorry that I cannot fully understand all the questions you asked. Pls let me selected those I understand to answer

3) Wafer will Epi layer usually has a very heavy doped substrate, which means low resistivity substrate. As we all know that layout up are due to the voltage drop acorss the substrate, which triggers the parasitic BJTs action. So, by reducing the substrate resistance with Epi-layer, the latch up problem can be minimized.

5) Depends on which technology you are refering to. CMOS usually uses (100), BJT uses (111). The reason of CMOS taking (100) is the oxide formed by (100) has less interface states comparing with (110) and (111). As known for long time, surface state is the killer of MOS devices.

For BJT, the reson of using (111), pls correct me if I am wrong, is that it has the highest oxide growth rate, which does help the through-put in mass production.

Hope it helps
Scottie

Re: ic's questions

ans 1) pad oxide protects the Si surface from the mechanical stresses induced by subsequent processing.
ans 2) To form LDD transistors use an oxide side wall spacer to self align the two drain diffusions enabling precise control of the width of the drift region.

Re: ic's questions

5. The problem may take place in caseof the <110> plane during diffusion as it cause channeling problems. Concerning <100> and <111> planes, we may use both but usually rate of etching in case of <100> is lower than (slower) the <111> this is an idea used in some MEMS applications.. I can give some other details but i don't know if i am speaking in the direction you need or not.. tell me to continue ..

Rabbena ma3ak..
Good Luck
Ahmad,

Re: ic's questions

<100> orientation causes lesser treshold for mos devices and less interfce stress.