Help me design a CMOS Inverter from scratch

Hi all
Am a freshie and new to designing and have to design a CMOS inverter from scratch...a full custom design ..cannot use standard cells...in other words i have to design an inverter and some other logic gates and incorporate them together to form a flip flop and in turn an asynchronous counter...a bottom-up design...
My system should work at 300MHz and the only other spec i have is that the rise/fall time should be 2ns.
My inverter as i stated earlier could be driving single or multiple other gates. How do i approach the design for the required W/L ratio??...wat should be my starting point??..i've read a couple of books and i always get stuck at trying to determine the value of the load capacitance for my design...i deduce that if i know that then i could do my design. also is it true that for a symmetric inverter i can assume my 'tphl = tfall/2' and similarly for the low-high transition..
I'd really appreciate any guidance related to this.
-the wabbit

cmos inverter design

Digital Integrated Circuits A Design Perspective(Senond Edition), Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic

ads cmos inverter design

Thank you for your reply...i think i have referred that book but am still confused...let me rephrase my question...i wanted to know how to determine the load capacitance if i'm designing the inverter as a stand alone cell cause i think once i know that and the i/p rise fall time..i should be able to determine the propagation delay and correspondingly the W/L..
Regards,
-the wabbit

cmos inverter design w/l

the load capacitance depends on the circuit it drive
so, first you must know how much circuits it will drive

propagation delay and fall time in cmos inverter

It has to drive the input of a NAND gate...can i take it to be driving another inverter??...also could someone please help me with the propagation delay relationship to the rise time question i'd posted earlier and how to determine the frequency...is it ging to be the inverse of the propagation delay...Thank you

CMOS Inverter design

in my opinion,normally the propagation delay and the rise/fall time are two parameters that have no directly relation, the propagation delay is for speed, while the rise/fall time is for signal quality, that the propagation delay is bad does not mean the rise/fall time is bad.
but for inverter, it is true, if the width of pmos is bigger, the rise time would be shorter and the output rise propagation delay would be smaller, the same is for nmos

Added after 7 minutes:

in addition, i guess the rise/fall time you mentioned is the output rise/fall time,
as for input slope( or rise/fall time), the propagation delay and the rise/fall time all depend on the input slope

Re: CMOS Inverter design

hI guys hope this help you

CMOS Inverter design

The propagation delay of the cell is related to the rise and fall time of the cell by this:
Tp = (Trise+Tfall)/2