addition & comparation in VHDL... help

vhdl addition

'a' and 'b' is std_logic_vector(3 downto 0), unsigned package included

b <= a + '1';

for the above addition ... the addition is done wth <a + "0001"> or <a + "1000"> ??

i do like tht n the quartus2 show no error...

'a' is 4 bits but '1' is one bits,,, but it can add together??.. does it not require the same width to add together?...

i try to read the arith package but i cannot seems to understand wad is written there,,, experiences is not enuff

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and for comparator... it compare from leftmost or rightmost?...MSB compare first or LSB compare first?..

thank you....

regards,
sp

vhdl signed addition

Good question!!!

b <= a + '1'; this will synthesize to incrementor

b <= a + '0001'; this will synthesize to an adder

Think about the actual hardware you want to implement and then write the Verilog
code to just describe the hardware.

This applies to ur comparator question also!
Hope this helps!

addition in vhdl

thank nand_gate for helping...

so if i just wanna add a one, so it make no diff in incremental and adder, right?

(a+"0001") = (a + '1') ???????

is it the same then??...

bcos if u wanna add a one to 32bits, then u would need 31 units of zeroes in front??

and and wad i meant in my first post is tht if u do
b <= a + '1';

it will do <a + "0001"> or <a + "1000"> ??
if '1' is also std_logic type...

many thanks..

regards,
sp

signed addition in vhdl

Regarding addition in VHDL:
1. The result of addition's lenght is the maximum length of the operands.
2. Adding is defined for signed, unsigned & overriden for std_logic_vector.
3. Operands must be of same type except adding to a constant as in your case.
4. The smallest operand will be expanded to match the size of the larger one according to the type of the operands. Signed are extended by ones.
5. Regarding your case: The '1' will be extended to "0001" to generate a 4 bit adder, but some synthesizers use reduction techniques , as gate gobblers, when it discovers that one of the operands is a constant. So, the final circuit will be an incrementor.

Regarding comparison:
1. Result is of type boolean.
2. As for addition.
3. As for addition.
4. No expansion in this case. ( 111 is > 1101).


Regards,
Amr.

vhdl if addition

thank you amraldo....

i understand even more now....

ieee.std_logic_unsigned.all is used....
a is std_logic_vector(3 downto 0)
b is std_logic_vector(4 downto 0)
so if (previous 2 posts hav errors... 'b' hav to be more than 'a' atleast one bit)

so the operation (0&a) + "11" is automatically change to (0&a) + "00011" ... true??

thank you...

regards,
sp

in 5 down to 0 what is the msb and lsb in vhdl

I guess from your final post you want to model a carry-out. The way you did is absolutely correct.
But what about modelling a carry in?
If you wrote:
--This may generate 2 adders althought you wanted one adder with carry-in.

To overcome use the following code:

vhdl signed unsigned addition

thank you for ur help.... i am not thinking on doing carry in anyway....

i am doing floating point multiplication.... just tht when i wanna add a '1' binary to a signal... i am lazy to type in so many '0' bits (32bits is wad i am doing )....

so i try wth a + '1' both hav diff length but no error... so i am wondering how the '1' can add to 'a' if 'a' is 4 bits... the '1' is interpret as 0001 or 1000...

but people keep on telling me other things..... hehehe

so i come out another one....a + '11'... so my question is 11 is translate to 0011 or 1100.... i read the arith package... n i almost faint i am still quite new to VHDL...

thank you everyone for helping,,, i am grateful...
but please answer my question...

regards,
sp