Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

guidance about designing the board more than 4 layers

Status
Not open for further replies.
M

mc&fpga

Member level 1
Joined
Jun 2, 2002
Messages
41
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
419
hi
who has experience in designig thge pcb for more than layers,
who knows a site or articles about the attentions in this designing.
for example which layer should be gnd and vcc
if we have more than 3 vcc what should we do?about clk and
ok,thanks
 

quidance about designing the board more than 4 layers

Look in the forum for Johnson's book on High-speed digital design for starters, and read that. But the layer stackup will depend on how many signal layers you need. If you have more than 3 VCC's, you will have to probably partition your planes into multiple power islands. Determine what VCC's are the most important and most used, and those should get a whole plane to themselves, or at least most of it. For clocks, it is important that the return paths are very clean, meaning that they should be adjacent to a ground layer, and have as few via's as possible. If it must jump from layer to layer, keep it always on layers that are adjacent to ground planes. These are just some rules to keep in mind...
 
Re: quidance about designing the board more than 4 layers

genrally for a 4 layer PCB, the much followed stack -up is
SIGNAL
GROUND
POWER
SIGNAL.

For designing a good stack-up, the key is in providing good reference for the signal layers.

Regarding routing the clock, signal , data, address traces etc, different designers tend to follow different techniques.

Most of them prefer to route the clock and the data and address signals inside the inner layers of the PCB (> 4 layers). In case of a 4 layer pcb, you are left weith no option other than to make use of the available 2 signal layers, to the best of your extent possible.
 
Re: quidance about designing the board more than 4 layers

hi,thanks
yes,they are some electronic rules for clock and vcc,&
buut i need more details and proffesional about these rules,for example:
if we use A/d or D/a
how should we connect DGND and AGND like these,
do you know articles about these designing and rules,
and where can i find the johnson's book that you said,
best regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top