fragnen
Full Member level 4
In a design we put logic for DFT and we call it design for test. For example we place AND gates in design to detect stuck at 1 fault.
What are the tools which can auto insert this kind of DFT logic in rtls or in netlist and in which phase of a design flow these kind of DFT logic can be auto inserted using such tools?
What are the tools which can auto insert this kind of DFT logic in rtls or in netlist and in which phase of a design flow these kind of DFT logic can be auto inserted using such tools?