Jordon
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Hi, I try to check the sram from tsmc's memory compiler mc2, by .gds and .spi, but the LVS reports give a mismatch error.
The SRAM is tsdn28hpcpa256x32m4mwa, and I disable some options when generting it, like BIST function..., the LVS report is :
Some warnings presented when running LVS:
I can not find any information about SDWA100W20_CNTDP_SVT on the internet. Although I believe the sram files from mc2 should be correct, but this mismatch, I dont konw how to fix it.
I have some guesses:
1. Is there some specific instructions, options in LVS for the SRAM? although I have not found the related notion in the datasheet
2. I have seen some posts for openRAM, they said LVS is not for layout without welltap or something like that, may I add some?
3. I have seen some posts about SRAM's LVS from VDD/VSS, although my report is not caused by VDD apparently, could this error be caused by the power connection?
Of course, there may be other reasons, but I don't know how to solve it. Can you give me some suggestions? Thanks a lot!
The SRAM is tsdn28hpcpa256x32m4mwa, and I disable some options when generting it, like BIST function..., the LVS report is :
Some warnings presented when running LVS:
I can not find any information about SDWA100W20_CNTDP_SVT on the internet. Although I believe the sram files from mc2 should be correct, but this mismatch, I dont konw how to fix it.
I have some guesses:
1. Is there some specific instructions, options in LVS for the SRAM? although I have not found the related notion in the datasheet
2. I have seen some posts for openRAM, they said LVS is not for layout without welltap or something like that, may I add some?
3. I have seen some posts about SRAM's LVS from VDD/VSS, although my report is not caused by VDD apparently, could this error be caused by the power connection?
Of course, there may be other reasons, but I don't know how to solve it. Can you give me some suggestions? Thanks a lot!
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