Current density of the transistor

Hello
my transistors in the output stage driver stage of the operational amplifier have a DC operating current of 3 mA.

According to my data sheet, the current density if the Metal 1 is 0.5 mA/µm.

The transistor comes by default with drain/source of 0.7 µm but with multiple contacts

Will the transistor experience the current density limitation?, if yes will it mean that I have to use multi-gate to increase the number of the drain/source for the same size ratio?

thank you

EM (ElectroMigration) current density rules are set for metal and via layers only, not for devices.
I guess, if you satisfy EM rules for contacts, your device should be fine.

timof said:

EM (ElectroMigration) current density rules are set for metal and via layers only, not for devices.
I guess, if you satisfy EM rules for contacts, your device should be fine.

Click to expand...

Thank you Tim for your answer,

but by the end the current is passing through the drain/source metal which is metal1, and here is my doupt, if the EM apply to metals it means it will apply to the source/drain,
once you get your contact from the transisor you will route with the width defined by the drain/source width. So even if you increase the mrtal route width, your bottleneck will be the drain/source... that is what i am thinking but need confirmation for it

Hi, May I know what is by default 0.7um?
what is the size of the transistor to carry 3mA current?

I suppose you size the width of the transistor to carry 3mA of current and this would take care of the EM. The minimum sized transistors and its contact are designed to carry a maximum current without EM, i guess.

Allowable current density depends on multiple things
- required lifetime
- device temperature history (you will pick a worst case or
someone will pick it for you
- metal composition ("aluminum" is rarely just aluminum
and alloy matters)
- step-coverage at topogtraphy
- via type (tungsten plugs are bad "heaters" and will ruin
"experiments" if run at excessive current density, to force
an outcome sooner, unless you do the work to determine
actual via-abutting-interconnect temperature (!= die, pkg
or oven temp).
- superseding specs which give you a simple limit and you
get to say "yes, sir!" until you complete your own verifiable
physics-of-failure journey

You should beware any foundry supplied "analysis" as these
IME carry loads of buried assumptions and poor attention to
detail. If you see an activation energy that looks like a
suspiciously round number (like "0.6V is the activation energy
for aluminum"). A righteous electromigration study / qualification
would -extract- the activation energy, not pick one from a book
while neglecting the text's caveats.

But in the end there's a rule and there's a method and you can
bet on enough sandbagging in a foundry's rules that you'll
not be surprised if you just check the box after doing an
adequate width-for-current-at-max-temp survey. Note
"adequate", which is a challenge to determine in circuits
with high mix and varying output, supply currents that may
require you to assert a "use case" as well (do you know it?).

Junus2012 said:

Thank you Tim for your answer,

but by the end the current is passing through the drain/source metal which is metal1, and here is my doupt, if the EM apply to metals it means it will apply to the source/drain,
once you get your contact from the transisor you will route with the width defined by the drain/source width. So even if you increase the mrtal route width, your bottleneck will be the drain/source... that is what i am thinking but need confirmation for it

Click to expand...

Current density in M1 can be zero or near zero - if you route current vertically through a metal stack at low metal layers (M1, M2, ...) to the top metals - where it will be routed laterally (top metals have much lower sheet resistivity).

To the contrary, all current going through device (channel) should go through the contacts - so current (density) in contacts is a much better indication for current density in the devices.
Hence, it's sufficient to check current density in contacts, to guarantee that the device should be fine.

Thank you guys for your explanation and your effort to help me.

please consider the image below, I have extended the drain and the source as they are the Metal 1 (M1) routes needed in my circuit, you see the route width is 0.7 µm, and I have stated in my first post, the current density for M1 is 0.5 mA/µm, which means that basically and in a simplest form this routes can pass maximum of 0.35 mA.
However, the transistor is supposed to have ID=IS= 3 mA. you see the problem, I am unable to route the 3 mA of the transistor because of the limitation of the routes.

I have tried to increase the width if the drain/source above 0.7 µm but the technology I use doesn't give me this option.

Have a look at "I/O" devices. A high current trace probably is pad connected, right? ESD rules may add salicide pullback for ballasting and there you can widen metal a lot.

That's why people make multi-finger devices - see a snapshot below.

Also, very often, if you have more than one metal layer - use lower metal layers (M1, M2, ...) to hook up your devices and route the current vertically to the upper, thicker, lower-resistive layers, for lateral routing.

Very often, people use a combination of these approaches - multi-finger devices, using lower metals for vertical current routing.
ANd if it's a high-current devices (power FET, ESD device, etc.) - use trapezoidal or more complicated shapes for the top metal layers, to reduce Rdson, and to make current density lower to avoid EM violations.

Thank you friends for your help and nice explanation,

I found the solution of multi-finger is very useful and solved my issue,

Thank you once again

Best Regards