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design of 2 stage opamp (350nm)

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Hello everyone,
I am new to the field of IC design and I have to build a 2 stage opamp in 350nm technology, but the catch in this is I have to build it with only NMOS.
I have approached it the conventional way of doing it with a single-ended transistor for each stage.
But I am unable to figure out how am I supposed to calculate the W/L ratio matching my specifications for the same.
It would be great if someone could guide me with the same.
Thank you

for reference, I'm attaching the link to the research paper that I am currently referring to.
Y. P. Tsividis and P. R. Gray, "An integrated NMOS operational amplifier with internal compensation," in IEEE Journal of Solid-State Circuits, vol. 11, no. 6, pp. 748-753, Dec. 1976, doi: 10.1109/JSSC.1976.1050813
 

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I suggest you review your FET theory of design before you do this to understand how W/L affects everything from gm or RdsOn and Cgs,Cdg, Cds or Ciss and Coss.

But while you do this , also ask for the specs of input/output impedance and gain BW.
One must always create specs or expectations and assumptions before any design.

Academic papers are often poor about this fact.
 
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This was my simplest 2 stage CMOS amplifier when I used a CD4000 series unbuffered inverter chip 40 yrs ago.

Now you need to do something like this with just 2 NMOS by device characteristics.

This is just a simulation. But we knew back then Fairchild & Harris parts were fastest and Motorola, NSC were slowest. Now these companies and their patents are owned by Motorola, now called "onsemi".

1632517588898.png



This is not accurately reflecting any CD4000 series but similar. Vin =10mVpp , Vout= 3.2Vpp

Note that in CMOS there is partial shoot thru during transition but not at low Ron, so the Zout does not shift as much. However this is supply sensitive. The closer Vt is to Vdd/2, the higher the dynamic range of Ron and thus gain.

Beta = 0.05 Vt=1.5
 
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