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Synthesis using additional spectre netlist?

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Hello

Usually in synthesis ( cadence genus tool) we use a verilog netlist, .lib files and perform synthesis to determine the timing paths for a design.
But now I want to perform synthesis / timing analysis using cadence genus tool using an additional spectre netlist( reliability / aging netlist) .
Aim is to determine the timing due to aging? Is it possible to include a spectre netlist too in cadence genus tool? Please advice me on the same.

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it doesn't make sense to synthesize a "spectre netlist" because that one would already be described at gate level or even more detailed. are you sure you really need to do this? did you design a circuit schematic by hand?
 

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ThisIsNotSam said:
it doesn't make sense to synthesize a "spectre netlist" because that one would already be described at gate level or even more detailed. are you sure you really need to do this? did you design a circuit schematic by hand?
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Yes I am not sure either about this either. But I do need to check timing using verilog netlist , .lib (liberaty files) and spectre netlist. Yes the schematics are designed by me .
 

I can't imagine performing timing of digital circuit by analog simulation.

I believe that what you need is to generate .lib files with aging, and then used them in synthesis tool.
 
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