Cheapest architecture for 8 megapixels mipi csi frame grabber (<1fps)?

What are best FPGA/CPLD options to build such frame grabber?
Requirements:
- support for 8mp mipi csi camera sensor, sony imx series or similar high resolution sensor
- no frame preview is required (no screen), only raw mipi csi data without processing
- save single frame to internal RAM on trigger signal with low latency, trigger signal speed may be around 1 FPS or slower
- built in or external DDR frame buffer
- readout of frame-buffer using slow interface (spi, rs232, etc.)

Is it possible to build using cheapest Lattice's machxo2 or machxo3 or similar FPGA product with some DDR memory?
Need some bare-bone architecture: after power up mipi csi camera sensor is configured to output continuous stream. On a trigger signal, one frame of this stream is saved to RAM in raw format. External PC read-outs this raw frame buffer through slow speed interface and perform further processing.

Hello,

maybe such adapter card would be helpfull:

https://reference.digilentinc.com/r...cam-adapter/reference-manual?s[]=mipi&s[]=csi

Theoretically it is compliant widh MIPI CSI-2 which is supporting 8K resolution.

As FPGA board you can buy for example:


It has on-board ZYNQ xc7z010 SoC (Hard processor+ FPGA array) and 256MB DDR3(1066) memory, what should be enough for such project.

Best Regards