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output resistance of R-2R ladder

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yefj

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Hello,giving the R-2R DAC bellow from each bit we see 4K 4K 4K as shown bellow.
So we get the same resistance structure thus current divide is the same and i cant get dirrent current form each bit.
Where did i go wrong?
1601837453093.png

1601834839437.png
 

@brad: These switches are switching current sources, injecting well defined current with high source impedance.
@yefi: I'm not sure what the question is.

I think, the Iout side of the ladder isn't correctly terminated.
 
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IOUT will only be correct when it's pushing
into a virtual ground. However when used
as part of a SAR ADC, accuracy does not
matter except at that virtual-ground point
(or -reference point, which reference must
also be applied to the R-2R ladder reference
point, shown as VSS here).

Now, those FET symbols are ones I'd take to
be NMOS, if so then the whole thing will not
be working as planned. It needs PMOS devices.

It would also be good if the set current was
scaled to match the resistor values. I do not
see this shown. A DAC I'm familiar with, had
another replica current sink mated to a 10K
trimmed resistor, along with two identical
pinned out 10Ks also trimmed to value, for
the output network (unipolar uses one,
bipolar uses two, or maybe the other way
around, it's been a couple of decades).
The R-2R ladder was same-species but
untrimmed resistors, a "good enough" match
to the current sources' setpoint.
 

FvM said:
@brad: These switches are switching current sources, injecting well defined current with high source impedance.
Click to expand...

Yes, a many-legged current mirror. I agree it should work provided similar current levels are present in the resistors too. This is possible with a supply voltage of several volts (maybe 5-10V).

However if supply is very low (say under 1V) then output is lopsided and non-linear (especially when switch b3 closes causing output to see supply V through very low ohms).
--- Updated ---

-------------------------------------------------

And returning to the schematic, looking at the resistor values to ground I believe they should all be the same.
 
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Yes, the MOS transistors have to be PMOS, of course. How about making the termination resistor 4R instead of R?
 

Hello, Yes its PMOS and R=4Kohm.
I have tried two cases 1000 and 0100 as shown bellow.
Equivalent resistance was made in both of them ,an i have problem to unravel it back, to get I_out from this current source?
What is the strategy for getting I_out?
Thanks.
1601901274861.png

1601901661918.png
 

This schematic simply has no right to work as linear DAC.

Current mode R-2R can work only as current divider, so full scale current is provided to MSB vertex of R-2R ladder, and output current is going into virtual ground (both output and complementary currents). The other possibility is to use R-2R ladder to degenerate current source array.
 
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How do i unravle the current back i I_out from the expression i shown above?
So i could i see difference currect from different bit.
Thanks.
 

Your transistor icons are upside-down Nmos.
P devices have the arrow oriented the opposite direction.

The R2R schematics I've seen have each bit delivering a high or low voltage to the network. (In other words, via half-bridge.) Your arrangement applies a high to each bit node, while providing continual path to ground (low voltage) through a resistor. It's unconventional although it may be simpler.

Bits turn On and Off in various combinations. As node voltages change it causes current to go one way then the other, and at changing mA levels.

Here's a condensed simulation showing the resulting output ramp as the binary count goes from 0000 to 1111. Steps are reasonably equal although not precisely. Anyway, it's only a simulation.

R2R DAC demo 4-bit counter diodes resis 2k 4k.png
 

maybe like this in the attached file
 

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Hello Sutapanaki, In the document we have a point where we have 2K and 2K with one node in common.
We could see it as 2K||2K=1K
Why you interpret the total resistance is 2K?
Thanks.

1601977917264.png
 

Thanks ,i understood the dinamics.

We get the highest current on the left side (so its the MSB there) and lowest on the left side (LSB is there)
 

yefj said:
Hello Sutapanaki, In the document we have a point where we have 2K and 2K with one node in common.
We could see it as 2K||2K=1K
Why you interpret the total resistance is 2K?
Thanks.

View attachment 164577
Click to expand...


It's a Norton equivalent. You remove the current and look what resistance you see. You see 4K. Then the equivalent current is the short circuit current in the right mot 2k when its right terminal is grounded.
 

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    yefj

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For cheesy sleazy perfboard DACs I have used
74AC series logic gates with binary weighted
resistors to a single summing node (OUT) and
no R-2R, giving a voltage range from VSS to VDD.
I like to use 10K resistors in series or parallel, this
is well higher than the on resistance of a 74AC
output driver and seems dead linear.
 
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Hello, from the output we see 2K and the whle network which I think its 2K equivalent so the output resistance is 4K.
another theory says we see 4K from the network and 2K in series so its 6K output resistance?
What is the correct version?
Thanks.

1602083741699.png
 

Looking from Iout to the left you see 4k
 
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So Rout is 4K.
Thanks.
 

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