pipeline ADC vs SAR ADC timing

assume we have pipeline ADC on N members each one bit
and we Have N bit SAR ADC.
IN SAR ADC our timing is 1SH time (sample and HOLD) and N bit charge redistribution each are the same.
so it T_SH+N*T_bit

in pipelineWe are sampling once too and passing the residue threw N stages
so Why Pipe line hase better timing?
Thanks.

Because pipeline is working a different sample at every
stage and marching them on out. First sample latency
(for 1 bit per stage) is same as SAR more or less, but
after pipeline is filled you get N times higher digitization
BW (one cample per clock, not one per N clocks).

Pipe line latency works on residues(not a different sample)
Both SAR ADC and pipe line Sample signal ONCE
In sar ADC we have N redistrubtions for each bit switch
In pipeline ADC we have N latencies.
So they preaty much the same.
i cant see the big advantage in pipeline?

Actually, no. Pipeline ADC samples on every clock and the sample propagates through the pipeline. For example, if we take sample number N by the S/H, then stage 1 of the pipeline works on sample N-1, stage 2 works on sample N-2, stage 3 works on sample N-3 and so on until the last stage, say, stage k works on sample N-k. On the next clock, sample N-k is produced at the output and stage k gets sample N-(k-1), while the S/H takes sample N+1, at the same time as stage 1 starts working on sample N. So, at every clock there are k samples in the pipeline and the output of the ADC spits out data at every clock. In this way a particular sample propagates through the pipeline in k clock cycles which is the latency, but the throughput of the ADC is at each clock cycle.
SARs have to wait for k clock cycles every conversion before producing the result. So, in a way they have latency of k clocks but also a throughput that produces data every k-th clock cycle.

So for each sample and hold of SAR time we need to wait another n*bit conversion time for every tick.
but in pipe line we are constantly priccesing samples with stage latency between every new proccesed bit .
Thanks

Yes. The only exception in the case of a pipeline ADC is when it initially starts working while the pipe fills up. That is, only for the first sample we have to wait for it n clock cycles because there is nothing before it.