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Assigning to a parameterized 2d Verilog array

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shaiko

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Hello,

I have a Verilog array defined as :
logic [0:num_elements-1] [element_width] some_array ;

I want to assign every array element with a vector that is all ones: "11...1".
I tried this but I get an error:
Code: 
some_array <= { num_elements { element_width { 1'b1 } } } ;
What's the correct syntax ?
 

I am not a Verilog guy.....

But can't you assign each elements of the array inside a double-loop?
 

I can, but I'm looking for a single liner - like VHDL's :
Code: 
some_array <= ( others => ( others => '1' ) ) ;
 

Just assign it directly as you defined it as a packed array format

Code Verilog - [expand]
1

some_array <= {num_elements*element_width{1'b1}};

--- Updated ---

If you had defined it using an unpacked array format then you would use a for loop to set each element.
 
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