How to apply automatic clock gating partially

I'm synthesizing an IP for ASIC, using Design Compiler. When using automatic clock-gating (with the compile command), the post-synthesis functional tests seem to pass for all the sub-modules, except for one which doesn't compute correctly (I still didn't find what exactly is the problem, but from a first glance, the Ready/Valid interface managed by an FSM doesn't seem to respond properly).

The particularity of this module is that it is iterative (computes DIV and SQRT) and the number of cycles computation takes is variable. Wheras all the others have a pre-defined number of pipelines.

According to the constraints report, all the constraints seem to be met.

1- Is there a way to check if the clock-gating has been performed correctly?
2- Is there a way to apply auto clock-gating partially i.e. apply it everywhere except that sub-module. ?

1 - the chances that the tool has a bug in clock gating implementation are zero. I would not spend time investigating this. you can, however, report how many flops were gated and how effective it was.
2- yes, with attributes. but then again, I doubt this is an issue.

ThisIsNotSam said:

1 - the chances that the tool has a bug in clock gating implementation are zero. I would not spend time investigating this. you can, however, report how many flops were gated and how effective it was.
2- yes, with attributes. but then again, I doubt this is an issue.

Click to expand...

Thanks for the answer. The gating report shows that only a few 1-bit and 2-bit signals haven't been gated because of bitwidth being < 3. Some other registers haven't been gated because they're always enabled. Overall it's about 98% gating. That's okay I guess?

For now, there is 1 operation (1.0 divided by 4.0) that provokes this problem with my iterative floating-point divisor block. I played around with different parameters (minimum bit-width, multi-stage, ...). I spotted some differences in the behavior between gated and ungated circuits, and that came from an 'always_ff' block where some if conditions were checking two or many signals at once (e.g., if(EN1 && EN2)), where a signal is supposed to be the delayed value of another one, but that value does never get memorized. So I tried to apply Multi-stage clock gating, and this didn't work and caused many other signals to be undefined (Z). Also, Hold and setup values are both set to zero by default (and I'm using the WL_ZERO wire model). I also modified the reset sequence without effects.

Without further context, I would guess your gate level simulation is not accurate. It is very unlikely that only one operation would fail, there must be many others that fall in the same case... which looks like a long path of sorts that your simulation could be mishandling.