open drain terminal of an nmos

if drain terminal of an nmos is open and source terminal is connected to 1v+ and the gate is also biased to a positive voltage VG, the Id=0 and Vds=0. can anyone explain? especially "Vds=0" I thought when a terminal is open it means we don't know its voltage, how does it say: Vds=0??

If VG is high enough (VG > Vs + Vth), the nmos is driven into "on" state, meaning Rds is low. Then an open drain (Id=0) results in Vds=0 , drain is at source potential (+1V).

When your gate source voltage is sufficiently positive, your nmos will be in inversion and capable of conduction. Your drain terminal will be connected to your source terminal through your nmos. If you leave the drain unconnected, any difference between source and drain potential will cause a current to flow so in the end the drain to source voltage will be zero.
I assume you are reviewing some simulation results. Your simulator will probably insert some very small conductance gmin between your drain terminal and ground and possibly across any junction. There will be parasitic elements across your gate oxide to model leakage current and possibly breakthrough. These elements will cause the source drain voltage to be nonzero in some cases. Temperature is a also factor in what kind of results you will be getting. Have a look at your netlist to see the parasitics. You won't see gmin in your netlist but your simulator will probably allow you set it to zero in the options somewhere.

Erikl was quicker to reply. His post says it all.