OD (drain) layer in TSMC 65nm

When using the tsmc 65nm, I see two ordinary diffusion (OD) layers. One of them under the 'purpose' column it says 'drawing' and the other one is 'drain'. I am totally familiar with the 'drawing' one but I dunno what is the purpose of the 'drain' one. I just looked at an existing example of an nmos device and noticed that the 'drain' OD layer is used on the drain region of the transistor. I will be grateful if anyone can provide more information on that.

I'm not 100% sure as I currently don't have access to documents of 65nm, but there may be cases where they needed DRC tool to know which diffusion is the drain. So they may have added it for this reason. For example an extended drain or a lightly doped drain device may have different rules which requires identification of the drain. Otherwise most devices are usually treated as symmetric devices and won't be checked properly, depends on how they implement the DRC rules though.

Anyway, I can't say things with confidence, but check your process document for rules regarding this layer. You'll get something out of that search.

Edit: It's usually not an issue for LVS to solve these, but for devices that aren't symmetric LVS rules may actually use this layer as well. Even the symmetric devices may use it, it again depends on how they implemented the ruleset. For maximum confidence draw your own device without it and check if it passes DRC and LVS.