Overlap DRC error in Eagle PCB

In Eagle PCB I try using vias to route the signal to bottom layer to avoid "trace overlap" on the top layer (as in the attached picture).
But now for some reasons I get overlap error on the vias.
I played with many clearance, distance, and size values in DRC settings, but none of them help.
Please let me know if you have any idea how to solve this, or just have to ignore the errors.

Looks like you put he via manually. When you place a via using the "via" tool, Eagle creates another "net", unless you put it exactly where the top and bottom lines joint. Putting a via at the right spot can be hard if you're not using a grid.

The best way to use vias when routing traces is clicking with the middle button of the mouse. This is a layer change tool. Doing this, a via is placed automatically. You can see that when you're using "route" tool, at the same bar where you choose trace's width and style, there are some vias option. This option are for the auto vias that Eagle will place.

Many thanks! Placing vias in auto mode solved the issue.
I think this is a bug in the program. Eagle should be smart enough to allow you to put in the right place the vias in manual mode also.

I have another question please. The rectangle surrounded by the ground in the attached picture it is the end of a transmission line.
I want to connect ONLY this end of the transmission line to the top ground.
I cannot connect this end of the TL to the ground in the schematic, because the program it will put on the layout ALL the sides of the TL to the ground. So I have to do this connection only in the layout mode.

If I use a rectangle or a polygon to do this connection works, but from the moment when I press "ratsnest" this will disappear.

If I use a wire to connect to the ground (as in the picture) works, but I get a "clearance" error.

I have an option to place a vias, but this will connect the end of the TL to the bottom ground, and I want to be connected to the top ground.

I don't know if is any other option.

Hi,

With EAGLE you can set a via to join the two traces, but you need to place the via exactely on the trace.

I assume you first placed the via somewhere else (the via gets a new signal name) and then moved it to the trces you wanted to join.

Klaus

I just did what you recommend and I get "clearance" error.

You did not provide any information concernig the net signal assigned to each one of both objects.

Hi,

In your picture it is clearly visible, that the via is not on the center of the blue line.

You could use the NAME command to give the wire and via the same signal name.

Klaus

I provided above all the necessary information.
This is a transmission line footprint, and the issue is that I cannot connect only one side of the TL to the top ground in layout. If I define the line in the schematic with the net signal GND, it will connect all the sides of the TL to the ground. I have to do this connection only in the layout mode.

I made the via bigger and centered to the blue line, and I get the same clearance error.

Anyway thanks, I got other information that Eagle is a pain if you want to do modifications only in the layout mode. Is not like other programs which allows to design a PCB in layout mode, without any schematic. This is a prototype and I will let the transmission line open. And when the PCB is done, I just solder to the ground the TL. Is not a big deal.