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Dual Boost PFC's interleaved in 10ms slots for noise reasons?

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treez

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Hello,
We are doing a 3.8kw Boost PFC stage. We are interleaving two PFC’s, each is on alternately for 10ms, then off for 10ms. The reason for this is because it will mean less noise problems, do you agree?
LTspice sim and schem and inductor currents attached
 

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  • Dual PFC CCM BOOST _LT1248_3.8kw_LATEST.txt
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  • Dual PFC interleaved _waveform.pdf
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ie, instead of having eg a FAN9672 style interleaved pfc, where they are interleaved inside the switching period, and both of them run at the same time, and the single controller has the difficulty of having to measure voltage across two sense resistors in amongst the noise of 2 pfc stages working simultaneously....
FAN9672 interleaved pfc controller
https://www.fairchildsemi.com/datasheets/FA/FAN9672.pdf
 

The reason for this is because it will mean less noise problems
Click to expand...
Why, particularly?
 
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Well, just imagine with the FAN9672 dual interleaved PFC chip, you have two low side sense resistors needing to be routed back to the same control chip …..how do you properly do that?…its not really possible, because the ground terminal of each sense resistor, and the ground terminal of the FAN9672 need to be the ‘same’ ground place, …and that will be very difficult for the PCB layout. And when you think of the switching currents going through both of those sense resistors..its asking for trouble with noise…why not just have one pfc stage working for 10ms, then off, then the other one starts up, which means that even though there are two PFC stages, only one is ever working at any time…surely this is more likely to result in less noisy operation.?
 

This ap note tends to agree with you on lower EMI with an interleaved PFC.

Page 5-2, basic concept.
Page 5-4, EMI, frequency and filter.
Page 5-5, More on EMI filter.

Page 5-14, CONCLUSION.

"Interleaving PFC pre-regulators has many
benefits. It can reduce EMI and boost inductor
magnetic volume. The amount of reduction
varies and depends on the design requirements
and design tradeoffs."
 

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Interleaved PFC (according to the usual meaning of the term) will surely improve EMC because the input ripple is cancelled or at least considerably reduced.

Alternating operation ("interleaved in 10ms slots ") of two PFC switchers as described in the first post doesn't seem to have any EMI related advantage.
 
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Interleaved PFC (according to the usual meaning of the term) will surely improve EMC because the input ripple is cancelled or at least considerably reduced.

Alternating operation ("interleaved in 10ms slots ") of two PFC switchers as described in the first post doesn't seem to have any EMI related advantage.
Click to expand...
I absolutely agree with you.
The problem is, when you are dealing with high power PFC stages of 3kw, and you are limited in PCB board space, one simply cannot afford the space to be able to correctly lay out properly interleaved PFC stages such as the one with the FAN9672 chip.
Instead, one is better off having two PFC stages which never run at the same time, but which alternate over 10ms intervals....purely for the sake of noise free operation due to the difficulties of proper PCB layout with properly interleaved stages.
Can you imagine trying to route two noisy sense resistors back to the same chip?..it would be horrendous. The two PFC stages would end up interfering with one another...unless done in the "10ms" way...surely you agree?
 

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