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You have to delay the FPGA and select what code should be used, Or doing a small CPLD device that plays a FPGA 2, and changes places in the jtag line, and then always program "both" FPGAs, But simply bitwise tell the CPLD where on the JTAG line it stays.
Look into multiboot support for the FPGA you are choosing. For Xilinx look at XAPP1246 for 7 series parts. Altera has similar support for this type of feature.
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