preethi19
Full Member level 5
Hi i am learning to do layout design in cadence and i saw one example. I have attached the schematic.
and the layout for the above schematic was given. I was able to understand everything except where for the resistor (poly resistor) in the layout they connected the drain of pmos and nmos to one terminal of the res and the other terminal of the res to the capacitor just as in schematic. And all this was fine. But then around the poly resistor an nwell was created. and then to the corner a nplus layer was formed. and from this nplus layer a metal connection was given to VDD. Why was this done??? What is this third connection for the resistor to the VDD while there is no connection in the schematic??? Its confusing. Pls help
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This is the resistor part of the layout. One terminal to the left is from drain of pmos and nmos and to the right is connection to capacitor. What about the third connection????
and the layout for the above schematic was given. I was able to understand everything except where for the resistor (poly resistor) in the layout they connected the drain of pmos and nmos to one terminal of the res and the other terminal of the res to the capacitor just as in schematic. And all this was fine. But then around the poly resistor an nwell was created. and then to the corner a nplus layer was formed. and from this nplus layer a metal connection was given to VDD. Why was this done??? What is this third connection for the resistor to the VDD while there is no connection in the schematic??? Its confusing. Pls help
- - - Updated - - -
This is the resistor part of the layout. One terminal to the left is from drain of pmos and nmos and to the right is connection to capacitor. What about the third connection????