1.2V mos in 2.5V OTA

Hi all, for a project I need to design some very low noise OTAs for up to 10MHz, in UMC65nm, supplied by around 2.5V. Using 1.2V mos devices is attractive, and the small signal simulations look good, but I'm not really comfortable with it. I don't think I fully understand the meaning of the different voltage levels and what operating conditions they refer to, and how flexible they are. Things are simple when you're just building logic gates, since your source and bulk will always be biased near a supply rail, but for an OTA this is not the case.

So what actually defines the proper operating limits of a 1.2V mos? Vgs, Vgb, Vdg, Vdb, Vds, etc? Should I be doing some large signal tests to ensure nothing terrible is happening? Maybe simulating the rise of the supply rails when powering on? How do I know what's tolerable and what isn't?

Yes, you need to do large signal simulations like power on, power off to ensure that the low voltage devices don't experience Vgs, Vgd and Vds more than their tolerable value (it is 1.2 V+10% in 1.2 V devices case I think, you can refer to the process document from your foundry).

If some transistor is seeing, say, 1.6 V during power on for a small time, then it does not mean that the device is going to blow immediately. It actually reduces the lifetime of the device to perform to its characterization.

+10% is a lot tighter than I was expecting. In my FDK, it actually includes models for 2.5V overdriven to 3.3V, but I believe those are meant mainly for use in I/O, not in analog applications. Can the Vds range at least be extended when using longer channel devices?

In my FDK documents I haven't found any specific explanation on the difference between the different voltage-rated devices, but I don't believe it's just a matter of different tox. Different doping levels, maybe?

In case of I/O devices, the 2.5 V devices can be over driven to 3.3 V, provided you keep a higher minimum length (500nm, if I am correct) than the other 2.5 V devices. I think, you can extend the Vds range a little if you are using a longer device. But there are no documents from the foundry that suggest to use longer 1.2 V devices to extend the Vds to a higher value. Yes, the 2.5 V devices will have a different doping concentration than 1.2 V devices, and that is also responsible for the different break down voltages.

Oxide break down voltage level is as high as 8 V. So, you can extend the Vgb upto 2-3V for 1.2 V devices without worrying. What you need to worry about are Vgs, Vds, Vgd, Vsb and Vdb. They are responsible for the break down of the junction diodes.

My input devices are pmos, so the source is tied to bulk. So my main concern is going to be Vds. Would bulk to substrate voltage also have a breakdown near 1.2V?

I'm doing some DC simulations with DC input applied and looking at device operating points, and I don't see any outputs which seem to indicate, one way or the other, the occurrence of breakdown in any junctions. I am given id, ids, igd, and igs, so I suppose from those I could estimate what my idb is from those? But that doesn't tell me how much of my ids is due to breakdown, is that even modeled in the saturation region?

nwell with p-substrate creates simple diode with quite high breakdown voltage - of course detailed value is provided by process docs.
The most important for You is to ensure Vgs and Vgd to be below max. process voltage (probably around 1.6V depending to many things, most of all to oxide thickness - also to be found in docs)

There are number of techniques to use thin oxide devices in circuits operating with much higher supplies. Look for an articles/book chapters of Rui Martins and/or D. Seo, Copeland about High-Voltage-Enable and High-Voltage-Tolerant techniques (since 2005)