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Current fed Full Bridge SMPS is not workable?

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treez

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Hello,
We are trying to design a bi-directional, isolated SMPS FOR 7kW.

We tried it with a Full Bridge, which in reverse direction, is a “Current fed Full Bridge SMPS” (as in the attached LTspice simulation and schematic).

However, as the LTspice simulation shows, its operation is ruined by 1.5kv overvoltage spikes on the drains of the Power FETs. This is caused by the sudden change of current in the leakage inductance of the full bridge transformer.

The overvoltage ringing is at 500KHz, -too low a frequency to be able to easily snub out. [frequency is too near F(sw)]

Do you know if this Current fed Full Bridge is really workable?
 

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  • Current fed Full Bridge SMPS.pdf
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  • Current fed Full Bridge SMPS.txt
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maybe such low freq appears because you put schottky diodes across power mosfets? why you did it? schottky diodes have rather big capacitance
 
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yes, my apologies, the ltspice doesn't have models of suitable voltage UF diodes. I am not sure that change would solve the problem though, at the end of the day, the leakage inductance is suffering a high di/dt, -the current fed full bridge looks like a bad topology to me....unless some kind of regenerative snubber is used, ?
 

maybe phase shifted FB will be better for you? for this topology ZVS can be archived, so no switching looses
 
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Yes its quite workable, but you need to think the whole thing in reverse.

What is needed is conduction overlap, not dead time.
All four semiconductors need to be turned on together for a brief instant during switching, to short the whole bridge out. Its current fed, so the current feeding the bridge never changes.

You cannot open circuit a current source, the resulting voltage spike would be deadly.

Its the exact opposite to a voltage fed bridge, where cross conduction shoot through, and the massive resulting current spike would be instantly fatal.
 
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What you're showing isn't a current biased half bridge. It's just a voltage biased bridge with a large inductance inserted. Obviously it's going to cause ringing, since it's effectively what you get when you lay out a half bridge with huge parasitic inductance and no bypass capacitors.

In a current fed circuit, the bias is implemented as a current regulated DC-DC converter. The bias will have bypass capacitors to smooth the ripple current from the bias source and snub ringing in the H bridge. This means that the impedance of the bias current is low at high frequencies, but that is necessary.
 
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thanks, that means we cannot make a full bridge smps bidirectional , because with the upstream current source converter ahead of it, that isn't likely to be bidirectional, and even if it was, we'd be best off having two full bridge converters, one going one way, and the other the opposite.....and switch the relevant one in/out according to the required direction of current flow.
 

The whole point of a current fed converter is to have overlap of the switching, this overlap period builds up current in the feeding L and allows a voltage boost, as long as the switches overlap there is minimal turn off stress, of course at some point you have to turn off or run at very low non overlapping PWM, the only solution is to have large zener like structures across each device or loss-less snubbers to move the energy to the o/p. These types of current fed converters are not intended for low power operation, they are for running at >50% (i.e. just overlapped) and higher, or off.
 

The thing is with current fed full bridge, is the spikes on the primary fets due to the leakage inductance in the transformer. These as you allure, require special active snubbers. The design of which is more difficult than the smps design.
(attached is ltspice sim of CFFB )
 

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  • Current fed Full Bridge SMPS _2.TXT
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Yes you need a very good low leakage design for the main Tx, and a clever low loss snubber to get the waste energy to the other side (o/p) for max efficiency...

- - - Updated - - -

a small high current cap on the bridge is useful too...
 

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