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SDC difference between commands

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shaiko

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Hello,

I'm wondering what is the difference between these SDC commands:
set output delay vs set_max_delay?
When should I use one and not the other?
 

set_output_delay is meant for the outputs from the FPGA. THey can be used to let the fitter change the delay on the output pins.
set_max_delay is to set the max delay between two items inside the FPGA - eg. between two registers.
 
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    shaiko

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set_output_delay is meant for the outputs from the FPGA
Click to expand...
Outputs from the device relative to a specified clock?

set_max_delay is to set the max delay between two items inside the FPGA
Click to expand...
Can it constrain the delay between a register and an FPGA pin ?
 

Allows you to override the default setup constraint for any path with a specific maximum time value for the path. You can specify the source (-from), common through elements (- thru), and destination (-to) elements of the path included in the maximum delay value.
Maximum delays are always relative to any clock network delays (if the source or destination is a register) or any input or output delays (if the source or destination is a port). Thus, input delays and clock latencies are added to the data arrival times; clock latencies are added to data required times; and output delays are subtracted from data required times.
 
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shaiko said:
Outputs from the device relative to a specified clock?
Click to expand...

As far as I understand it

Can it constrain the delay between a register and an FPGA pin ?
Click to expand...

I dont know - ive never done that. Ive only used set_max_delay for CDCs and to make the fitter prioritise specified paths (as a last resort)
 
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How do you constrain signals inside an inner hierarchy ? How do you access the internal element ?
 

shaiko said:
How do you constrain signals inside an inner hierarchy ? How do you access the internal element ?
Click to expand...

Either by using the entire hierarchical path name or use some wild cards to find the path.

e.g.

top/module1/module2/module3/some_reg_name

could also be found by...
top/*/some_reg_name
 
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ads-ee said:
Either by using the entire hierarchical path name or use some wild cards to find the path.

e.g.

top/module1/module2/module3/some_reg_name

could also be found by...
top/*/some_reg_name
Click to expand...

Be careful on the hierarchy paths - I dont know whether xilinx and altera use the same formatting. In Altera, the format is:
top\entity1_name:inst_name\entity2_name:inst_name\reg

Also, altera allows two wildcards, * (for multiple char replacement) and ? (for single char replacement)
I think Vivado only allows *, and currently has a bug where only a single * can be used in a path (you can work around it with regular expressions though).
 
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    shaiko

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ads-ee, TrickyDicky,

Can you please give me a brief insight on how you constraint your (FPGA) design:
Other then the trivial "create_clock" command for - what SDC commands do you most often use?
To what do you pay special attention?
 

Usually my timing SDC files look something like this:

1. create_clock
2. set_input_jitter
3. create_generated_clock
4. set_clock_groups
5. set_input_delay
6. set_output_delay
7. set_multicycle_path (if there are any)
8. set_min/max_delay (exceptions)
9. set_false_path (more exceptions)

I also pay special attention to having no unconstrained paths, and no/very_little overlap in constraints (i.e. I usually have a small number of very specific set_min/max_delay and set_false_path constraints in the SDC).
 
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    shaiko

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create_clock will constrain 90% of the design.
Then you need max_delays or false paths for CDCs
then IO delays with set input and output delays.

Other than that - go with whatever the documentation tells you.
If there is a timing issue (ie not meeting timing) first port of call is always the code.
 
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