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[moved] Synthesis RTL in synosys DC

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njr@1

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Dear All,

When we synthesis in Design Compiler with different clk period why does the critical path changes with the change in clock period ?
So does the area when viewing the report using report_qor.

Please help me understand this
 

When we change the clk period, the clock constraint varies. The required time for the arrival of signals from a register to another register without violations varies. So the drive strength of the cells varies. The tool will try to optimize the new constraint and will try to design accordingly. So the critical path varies. If you change the clock period, even the clock buffers and clock inverters in the clock clock tree gets changed in the new design.
 
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