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source latency will be same for all flops (source clock and clock on flops should be in same clock domain).
clock uncertainty will be calculated depend on the syntax you provided to the tool .. if you have given a constant number for all clock then it will be same for all flop ...
skew is the difference between the longest path from the clock source to the CK-flop less the shortest path from the clock source to the CK-flop.
skew = max_latency - min_latency.
Well the question is how STA interpret the clock latency, and my remarq is just to indicate how the latency is used, and why it could not be equivalent for all flops, because that'll means the skew will be equal to zero.
I believe skew is different than you described here .. from wikipedia -
In a synchronous circuit, clock skew (TSkew) is the difference in the arrival time between two sequentially-adjacent registers. Given two sequentially-adjacent registers Ri and Rj with clock arrival times at register clock pins as TCi and TCj respectively, then clock skew can be defined as: TSkew i, j = TCi - TCj
so it's not mean max latency and min latency ... there is difference between latency and skew , and both are different term ..
but relationship is close between latency and skew ..
1-What is for you "the arrival time"? For me that's the latency.
2-Skew could be global, usefull.
global= max latency- min latency
usefull is the skew calculating between two flops which have a common path.
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