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Hold Uncertainty for Logic Syntheses -> required?

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ivlsi

ivlsi

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Hi All,

Is it necessary to define Hold Uncertainty for Logic Synthesis? As far as I know, Hold Time violations should be fixed during P&R phase. So...

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Not required except the PnR tool used the generated sdf from the synthesis tool.
 
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    ivlsi

    ivlsi

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okay, thanks!
 

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