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Design this digital circuit

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sun_ray

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A 32 bit data is coming at 100 MHz continuously. This data needs to be read at 200 MHz with data width of 16. Please design a digital circuit for it.

Regards
 

It's a very simple circuit , since data rate is equal at both end , you can use 3 depth 32-bit buffer , 1 extra here added just for safety purpose.

one side write 32-bit data at 100MHz clock and other side read 16-bit data at 200 MHz clock.

Rahul J
 
rahul.achates said:
It's a very simple circuit , since data rate is equal at both end , you can use 3 depth 32-bit buffer , 1 extra here added just for safety purpose.

one side write 32-bit data at 100MHz clock and other side read 16-bit data at 200 MHz clock.

Rahul J
Click to expand...

Why will not a buffer of depth 1 serve the purpose? Do you want to mean a FIFO by buffer?
What will be the width of this buffer of depth 3?

What will be the solution if the 100 MHz and 200 MHz clocks are asynchronous? What will be the solution if the 100 MHz and 200 MHz clocks are synchronous?

Regards
 
Last edited:

sun_ray said:
Why will not a buffer of depth 1 serve the purpose? Do you want to mean a FIFO by buffer?

What will be the solution if the 100 MHz and 200 MHz clocks are asynchronous? What will be the solution if the 100 MHz and 200 MHz clocks are synchronous?

Regards
Click to expand...

FIFO is not required here.

Even if clock are synchronous , you need to use 2 depth simple buffer , here buffer means 32-bit register.

Reason is , there will be routing delay in clock, and there may be possibility you lost 1st or last data while reading and writing.

if both clocks are synchronous, then also 2 depth 32-bit register will work. since clock frequency is same , you just need to take care clock phase.

- - - Updated - - -

imbichie said:
Use a dual port fifo
Click to expand...

Dual fifo is not required, it will be waste of logic and area.
 
imbichie said:
What about if the clocks are asynchronous?
Click to expand...

Even if clocks are asynchronous, their frequencies having a relationship.

it's just divide by 2 clock , so here asynchronous mean , both clock phases are in unknown position , but whatever clock phase difference there after out of reset, will be maintained.

Let me know if you need more explanation.
 
Please be reminded that if you are working on protocol related datapath, it is not enough to only think about data bus. Usually data is guarded by a valid signal to indicate whether the data is valid in current clock cycle.
If that is true(meaning you are designing a protocol with hand-shaking signal(s)), you need control logic to decide when to read(or even write) the 2 depth buffer. You need to have a write/read pointer to calculate whether there is enough data to feed the 200MHz bus by read. This is why usually FIFO is applied.

Please ignore the above paragraph if you are not working on a protocol which demands some hand-shaking between transmitter and receiver.


sun_ray said:
A 32 bit data is coming at 100 MHz continuously. This data needs to be read at 200 MHz with data width of 16. Please design a digital circuit for it.

Regards
Click to expand...
 

This is continuous data , and data rate is same at input and output, please note here , even if you are working on such protocol, then next layer of logic suppose to handle this.

Using FIFO , I am again saying it's waste of logic here. even if you need to control input data and output data with enable signal, you can increase the datawidth by one and put enable signal along with data.

Using FIFO here , actually you are storing data based on input/output enable, and for that you can design the logic but not FIFO ..
 
When I said FIFO, I mean the philosophy of first-in-first-out, not a specific part of code that can be copied and pasted.
With the first-in-first-out request from the description, and with wr/rd enable, this design is literally a "FIFO" then.

storing valid signal into data buffer might work, only if the downstream logic accept this format. In some case, if the downstream logic demands continuous valid data for certain period(like within a frame/package), then you have to remove the invalid cycle in the data stream.

Again, this might not be what sun_ray is trying to achieve. But I remember sun_ray was asking some AXI design questions. And AXI is a protocol with handshake signals. In case he needs more information, the discussion might be helpful as well.
 

So designing a digital circuit is totally depend on specification, a complete specification is required.
 
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