[SOLVED] [Newbie Query] How to handle inherent concurrancy in VHDL

bitprolix said:

Hi All,

I'm a complete newbie and have just recently(a week back) started learning VHDL. I'm finding it very interesting and challenging as programming in VHDL is very different that other high level programming such as 'C'. I'm reading the on-line materials, but the amount of information that needed to be grasped is very huge, and because of that I'm kind of stuck in a small problem where I know that there is a problem but do not have enough language/semantics skills to fix it. Therefore It would be very helpful to me if you can throw some light here and give me direct or indirect pointers. The problem is as follows:
I've to implement a up-down counter by keeping the following in mind:

i) CLK (in): Clock signal. Counter counts on the rising edge of the clock signal.
ii) RESET(in): Resets the counter to the start address.
iii) ENABLE(in): If the enable signal is 1, counter is functional. Otherwise counter is stopped.
iv) STARTADR(in): Holds the start value of the counter
v) STOPADRR(in): Holds the stop value of the counter.
vi) ADDRESS(in): Represents the current output value of the counter.

The behavioural architecture for such counter is

Code:

architecture RTL of Counter is
signal counter : unsigned ( BIT_WIDTH -1 downto 0 );
begin

Cnt: process 
begin
	wait on CLK until CLK = '1';
	if ( RESET = '1' ) then 
		counter <= STARTADR;
	elsif ( ENABLE = '1' ) and ( counter < STOPADR ) then 
		counter <= counter + 1;
	elsif ( ENABLE = '1' ) and ( counter > STOPADR ) then
		counter <= counter - 1;
	end if;
	ADDRESS <= counter;
end process Cnt;

end RTL;

So far so good, Counter is counting in both directions :smile:

As I've understood, to test my design, I need a test bench which I can simulate using CAD tool. I have been provided a test bench to test this design and in the test bench, i see that there are deliberate introduction of delays and because of which, I see that the counter sometimes misses the rising edge of the CLK signal (please refer the screenshot below, where the counter was not incremented at the rising edge of the CLK signal at 70ns), Now to handle such delays (please refer the testbench code below) or the inherent parallel nature of the design model, how should I fix this ? Also, If possible suggest me the book that you found most useful when you started your career/research in electronic design.

Code:

Test_sequence:  process

    procedure MakeSequence
      ( constant START_VALUE, STOP_VALUE, CYCLES_COUNT : positive ) is
    begin
      wait on Clk until Clk = '1';
      Strt <= conv_unsigned ( START_VALUE, BW ) after 1 ns;
      Stp <= conv_unsigned ( STOP_VALUE, BW ) after 1 ns;
      Rst <= '1' after 1 ns;
      Ena <= '0' after 1 ns;
      wait on Clk until Clk = '1';
      Rst <= '0' after 1 ns;
      wait on Clk until Clk = '1';
      Ena <= '1' after 1 ns;
      for i in 0 to CYCLES_COUNT - 4 loop
        wait on Clk until Clk = '1';
      end loop;
      Ena <= '0' after 1 ns;
      wait on Clk until Clk = '1';
    end MakeSequence;

  begin
    MakeSequence ( 2, 12, 16 ); 
    MakeSequence ( 13, 5, 16 );  
    Strt <= ( others  => '0' ) after 1 ns;
    Stp  <= ( others => '0' ) after 1 ns;
    Halt <= true after 50 ns;
    wait;
  end process Test_sequence;

View attachment 96364

Thank you so much for your help.

Click to expand...

I see that the counter sometimes misses the rising edge of the CLK signal (please refer the screenshot below, where the counter was not incremented at the rising edge of the CLK signal at 70ns)

Click to expand...

you should do :

process(clk)

begin

if rising_edge(clk) then

bla bla la ....

end if;
end process;

Click to expand...

entity Counter is
  generic ( BIT_WIDTH   : positive );
  port (
    CLK                 : in bit;
    RESET, ENABLE       : in std_logic;
    STARTADR, STOPADR   : in unsigned ( BIT_WIDTH - 1 downto 0 );
    ADDRESS             : out unsigned ( BIT_WIDTH - 1 downto 0) );
end Counter;

--Register-tranfer level
architecture RTL of Counter is
signal counter : unsigned ( BIT_WIDTH -1 downto 0 );
begin

Cnt: process(CLK) 
begin
	if ( RESET = '1' ) then 
		counter <= STARTADR;
	end if;
	if (clk='1' and clk'event ) then
	   if ( ENABLE = '1' ) and ( counter < STOPADR ) then 
		  counter <= counter + 1;
	   elsif ( ENABLE = '1' ) and ( counter > STOPADR ) then
		  counter <= counter - 1;
	   end if;
	end if;
	ADDRESS <= counter;
end process Cnt;

end RTL;

also your up/down mecanisem look faulty.

Click to expand...

if (clk='1' and clk'event )

Click to expand...

--Entity
entity Counter is
  generic ( BIT_WIDTH   : positive );
  port (
    CLK                 : in bit;
    RESET, ENABLE       : in std_logic;
    STARTADR, STOPADR   : in unsigned ( BIT_WIDTH - 1 downto 0 );
    ADDRESS             : out unsigned ( BIT_WIDTH - 1 downto 0) );
end Counter;

I'm finding it very interesting and challenging as programming in VHDL is very different that other high level programming such as 'C'.

Click to expand...

VHDL is case insensitive, so CLK, CLk, ClK, Clk, cLK, cLk, clK, and clk are all the same signals.

Click to expand...

You shouldn't break the if into two different if statements (i.e. one for reset and one for the clk) it should have been elsif (clk='1' and clk'event) then. That will give you an asynchronous reset, which means you'll need to include the reset in the process sensitivity list.

Click to expand...

Cnt: process(CLK, RESET) 
begin
  if ( RESET = '1' ) then 
        counter <= STARTADR;
  elsif (CLK='1' and CLK'event ) then
        if ( ENABLE = '1' ) and ( counter < STOPADR ) then 
              counter <= counter + 1;
	elsif ( ENABLE = '1' ) and ( counter > STOPADR ) then
              counter <= counter - 1;
        end if;
  end if;
  ADDRESS <= counter;
end process Cnt;

end RTL;

bitprolix said:

But this still seem to be not giving a correct waveform :sad:

Click to expand...

FvM already mentioned that you've got an extra clock delay on ADDRESS due to having it assigned within the process

Click to expand...