Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] rising_edge() of switch....can we

Status
Not open for further replies.
A

ABO_ATHAB

Junior Member level 1
Joined
Dec 19, 2011
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,403
helloow
can we use rising_edge() and falling_edge() functions to detect rising_edge of the switch in spartan 3E ??
if not is their any method??

regards
m.s
 

Provide some more details .. insufficient .. are you coding some logic to detect that?
 
you could, but I would not recommend it. The rising/falling_edge functions treat the input as a clock, and in an FPGA you're only allowed to evaluate a single clock in any process.

It would be much better to have a system clock and a synchroniser on your switch (ie, sample the switch with the clock through a double register) and then do a rising edge detect on that.
 
What TrickyDicky said. Besides the standard drawbacks of using a regular input as a clock input, you have the extra bonus drawback of this switch being mechanical. And as such you'll probably want some debouncing. So as said you use a synchroniser on the switch input, and then do the edge detection after that.
 
thank for all for suggestion
but is thier a vhdl code for this words

""""It would be much better to have a system clock and a synchroniser on your switch (ie, sample the switch with the clock through a double register) and then do a rising edge detect on that.???"""
 

Hi ABO ATHAB,

What TrickyDicky and mrflibble said is correct. it will consider as clock. To avoid that you can use like below,

Let we consider signal which to be detected is a. Then make a delay wrt clock.Then delayed signal is a_delayed.
now to detect rising edge, if( a= '1' and a_delayed ='0')then.
to detect falling edge if( a= '0' and a_delayed ='1')then.
 
thank sureshaa
all to all how suggest the solution
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top