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MDAC problems in the pipelined ADC

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ronanchang

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I have some problems about the MDAC circuit.
The output values of MDAC should be stable in some periodes.
But the output values in my design alwayes have peaks.
And this will cause the following comparators fatching wrong values.
Can someone tell me what's the problems in my designs??
Thanks!!!!!
 

perhaps capacitance cause
 

The overshoot is due to poor phase margin of your loop composed from
Cin, Cf , Cload and OP. Check the phase margin at the output of OP.
 

first of all check ur opamp's stability.. if its doing well then check ur feedback switch resistance and try to reduce it.. as high resistance in series with the cap in feedback path causes a low freq zero. which can cause an overshoot..

bbye
 

Hi all

I have also problem with my MDAC.
I have designed a fully differential opamp with UGB=680MHz, DC gain=67db, PM=61 deg, input common-mode voltage = 0.75v but the output common mode voltage =0.5v .This opamp is designed for a pipelined ADC and is used in the MDAC. The signal CM is also 0.5 volt

The problem is that this opamp doesn't work! I tried to test it in a simple Charge-Redistribution SHA circuit with sampling rate of 4 MHz, but both of the outputs are always saturated in the hold phase and consequently the differential output is zero.

I know that in theory, the opamp of a CR SHA doesn't need to have equal input and output CM voltage. So what is the problem?
 

If your opamp is fully differential, do you have CMFB circuit for the output common mode? If yes, and if it's reference is different than 0.5v, check what happens with it and why it is not able to control the output common mode. Attaching a circuit will be helpful.
 

Your op-amp design doesnt settle in well before the value is fetched.

So either u can make ur switches smaller or ur capacitances larger.

This is my Amster project report on pipelined ADC design.
I have included as much schematics as possible.

https://jennisjose.webs.com/pipelinedadc.htm
 

Hi mohsen
It seems that CMFB ckt. is not working properly, CMFB ckt holds the CM o/p voltage against variation.Failing so, o/p either goes towards VDD or VSS.

regads
anil
 

ronanchang said:
I have some problems about the MDAC circuit.
The output values of MDAC should be stable in some periodes.
But the output values in my design alwayes have peaks.
And this will cause the following comparators fatching wrong values.
Can someone tell me what's the problems in my designs??
Thanks!!!!!
Click to expand...

I am enable to understand MDAC design and how to implement the switch in MDAC design , can u plz help me?
 

darshana kuche said:
I am enable to understand MDAC design and how to implement the switch in MDAC design , can u plz help me?
Click to expand...

Hi Darshan
In PL ADC, MDAC consists of Sub-DAC, 2X Amplifier with subtractor, all implemented through SC.
Switches can be implemented either by only nMOS or CMOS depending upon signal level.
 
Hi Every body
like some guys I have to design a pipeline ADC with 120 MS/s sampling frequency.
at first i designed an ideal pipeline ADC and it worked properly but when i want to implement Opamp it doesn't work but when i
decrease sampling frequency to 60 Ms/s it works and my ENOB becomes 11 bit.
Here i list some features of my pipeline and Opamp.
pipeline : Fs =120 Ms/s Res=12 bits
Opamp:gain=62 db bandwidth≈ 650 MHz slew rate=high enough P.M≈61°

could you tell me where my problems are?
best wishes
A.jafari
 

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