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Various instances present in the design

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HI ,

There is one simple question i would like to put up regarding the various instances present in the design.

What are sequential instances, hierarchial instances and combinational instances.

Basically my question is what are instances and how do they differ from pins present in the design?

what are hard macro pins, register pins ???

Please clear my clarification.

thanks
tanvi
 

Hi Tanvi

A cell is made up of transistors and has a defined functionality. So anything that is made up of cells which has a defined functionality is an instance. For eg. Consider a buffer. It is an instance made up of 2 inverter cells.

Sequential instances are flip flops present in your design or something that passes on data with clock pulse and can store bits, combinational instances are made up of combinational logic i.e. they are made of basic gates like and, or, nand etc.. which don't store any values.

Macro can be an instance in your design , and these can be used in multiple designs generally without any change. The pins of these are macro pins.
Registers are again your flip flops and its pins are register pins.

Hope this is clear.
 
hi jeevan,

i found it very useful but maybe i went wrong inframing the question,
i am a bit confused regarding the difference between ports and pins ?

can you please make me little bit clear on this also.

thanks
tanvi
 

Ports are used to define inputs or outputs at the top level of the hierarchy or in simple words, ports are used to communicate to the outside world or to the logic outside the current hierarchy. Where as pins are more internal or at the cell or instance levels. Nets are used to connect ports to the pins, or to the internal cells in the design.
 

Ports are used to define inputs or outputs at the top level of the hierarchy or in simple words, ports are used to communicate to the outside world or to the logic outside the current hierarchy. Where as pins are more internal or at the cell or instance levels.
Click to expand...

I wonder where you find this terminology? I'm used to an opposite meaning of the terms. The specifications of both Verilog and VHDL reserve the term "port" for the interface of a module respectively entity, which can either connect to the outside (top module/entity) or internally. In HDL specifications, the term pin exists related to I/O primitives, in other words, external connections.
 

FvM said:
I wonder where you find this terminology? I'm used to an opposite meaning of the terms. The specifications of both Verilog and VHDL reserve the term "port" for the interface of a module respectively entity, which can either connect to the outside (top module/entity) or internally. In HDL specifications, the term pin exists related to I/O primitives, in other words, external connections.
Click to expand...

I was referring to more of a back end terminology or from Physical design perspective where we have ports in top module and pins inside the module connecting ports and the cells.
 

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