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Synthesis mean only Conversion?

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maulin sheth

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Hello All,
What does synthesis mean?
Only conversion from RTL to Netlist or any else? And what is else?

Thanks in Advance.
 

In general logic synthesis refers to translating digital system description from a higher level of abstraction to a lower one. A HDL file needs to be compiled first giving us a RTL netlist of sort which the synthesis process will translate to a gate-level netlist.
 
Hey,

Synthesis is not just converting RTL or higher level design into lower level (mainly gate level). Synthesis tools like synopsys design compiler also do optimization of your design. There are various algorithms which are followed based on the design and constraints put by the designer. This is the reason it is always advised to do RTL coding in behavioral manner rather than structural manner. In case of structural modeling synthesis tool cannot do optimization as you have already provided the gate level view.

Best Regards,
Abhishek
 
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