sakthikumaran87
Full Member level 3
Hi Friends,
I have a basic doubt on setup delay. I know that setup is the amount of time before which your inputs should be stable so that it will be deducted by the rising edge of the clock. And if it happens in the critical window then it will lead to metastability.
But my concern is what is actually the setup in terms of analog parameters. I read in one of the previous posts that it is the minimum time for the input node capacitance to charge. If that is the case why metastability is created when it changes in critical window.
I remember reading once a pdf which considered a flip-flop to be having some comparator which will take long time to settle(leading to metastability) if the values changes in critical window and justified the need for setup delay. But i dont have the material to refer.
As for as hold is concerned, i can clearly understand that if hold is not met then FEEDTHROUGH will occur which is undesired and will make the chip fail. Hence the hold timing has to be met.
I know it is a pretty long post, but my intension is just to convey my complete understanding on the concepts, so that it will help you to review my level of understanding and correct me whereever i have gone wrong.
Kindly help me to understand this topic better.
Thanks in Advance,
SK
I have a basic doubt on setup delay. I know that setup is the amount of time before which your inputs should be stable so that it will be deducted by the rising edge of the clock. And if it happens in the critical window then it will lead to metastability.
But my concern is what is actually the setup in terms of analog parameters. I read in one of the previous posts that it is the minimum time for the input node capacitance to charge. If that is the case why metastability is created when it changes in critical window.
I remember reading once a pdf which considered a flip-flop to be having some comparator which will take long time to settle(leading to metastability) if the values changes in critical window and justified the need for setup delay. But i dont have the material to refer.
As for as hold is concerned, i can clearly understand that if hold is not met then FEEDTHROUGH will occur which is undesired and will make the chip fail. Hence the hold timing has to be met.
I know it is a pretty long post, but my intension is just to convey my complete understanding on the concepts, so that it will help you to review my level of understanding and correct me whereever i have gone wrong.
Kindly help me to understand this topic better.
Thanks in Advance,
SK