[SOLVED] Verilog Signed multiplication Help

Hi,

I'm new to verilog and have a question about signed multiplication. My program works for positive integers but fails for negative numbers.

Below is the code with test bench.

module multiplier(clk,X, h_0, h_1, h_2, h_3, h_4, Y);
input clk;
input [4:0] X;
input [3:0] h_0;
input [3:0] h_1;
input [3:0] h_2;
input [3:0] h_3;
input [3:0] h_4;
output [10:0] Y;
integer [10:0] Y;

integer [15:0] A;
integer [15:0] B;
integer [15:0] C;
integer [15:0] D;
integer [15:0] E;

always @(posedge clk) begin

A <= h_0 * X;

B <= h_1 * X;

C <= h_2 * X;

D <= h_3 * X;

E <= h_4 * X;

Y <= A+B+C+D+E;

end
endmodule


TEST BENCH!!!!!!

module tb_multiplier();

reg clk;
integer [3:0] h_0;
integer [3:0] h_1;
integer [3:0] h_2;
integer [3:0] h_3;
integer [3:0] h_4;
integer [4:0] X;

wire signed [31:0] Y;

initial begin
clk = 0;
h_0 = -9;
h_1 = 8;
h_2 = 7;
h_3 = 6;
h_4 = 5;
X = 15;

#500 $finish;
end


always begin
#1.6 clk = ~clk;
end

multiplier call(clk, X, h_0, h_1, h_2, h_3, h_4,Y);
endmodule


In the simulation (the H_0 = -9 ) is treated as a positive 7. The output is 495.

Does anyone know how to fix this?



Thanks in advanced

Declare your signals as signed, like so:

Thank you so much!!!!! I spent hours on this over something so simple. I thought specifying my variables in the testbench as integer Verilog automatically recognizes the value as signed.

When you make an assignment or port connection form a signed data type to an unsigned data type, the signedness of original data is lost. Only the individual pattern of bits is transferred.

Nice explanation::

dave_59 said:

When you make an assignment or port connection form a signed data type to an unsigned data type, the signedness of original data is lost. Only the individual pattern of bits is transferred.

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