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Single stepping in modelsim VHDL

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abhiverma812

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Hello,

I am relatively new to modelsim and VHDL language as well. However, I wanted to know if we can do single stepping while debugging our code in Modelsim, as is done in C programming. I want to see values of my signals/variables at each step I move to in my code.
I found how to do single step, however, I was not able to find where I can see values of signals/variables. Apart from this, is it possible to plot variables on waveform.?


Best Regards,
Abhishek
 

yes you can put variables on the wave window. you need to find them in the locals window.

as for single stepping, I'm worried you think vhdl is a programmjng language. signals don't update until a process suspends, so you may be a little confused if you watch signals as they update.
 

Single-stepping will advance 1 Delta at a time. You need to read up on Deltas but it's rare to use it. As said above, fatal to think vhdl as programming language. Think digital circuit first then represent it in vhdl, same as representing cct as schematic.
 

Hey,

Thanks for replying. I know that signals update after a process suspends. However, if I can do single stepping I can see variable values which changes at that time only. For signals, I can use step over ...which will take me out of that process once and hence I can see signals updation as well.

Can you please provide a little more details on local window and variables on wave window..??


Abhishek
 

from the menu -> view -> locals

You can now click on any part of the heirarchy in the sim window and the locals window shows you all the signals and variables local to that part of the heirarchy.
 
If your coming from a programming/c background, don't get hung up on using variables. In programs variables are the main way of handling data and doing things. In vhdl use signals for everything you can and variables only when you really can't use a signal for the job. That's why variables are harder to view in ModelSim etc than signals: signals are more useful and 'truer' to the language goals.

I take it your designs are running from a clock? You'll find it more helpful running your simulation for a clock time, or multiples of one, to usefully single step. If you've a 50mhz clock, do 'run ? ns' to get to the interesting bit then 'run 20 ns' 'run 40 ns' etc to step through it. That should give you what you're looking for.

Good luck :)
 
TonyM said:
If your coming from a programming/c background, don't get hung up on using variables. In programs variables are the main way of handling data and doing things. In vhdl use signals for everything you can and variables only when you really can't use a signal for the job. That's why variables are harder to view in ModelSim etc than signals: signals are more useful and 'truer' to the language goals.

I take it your designs are running from a clock? You'll find it more helpful running your simulation for a clock time, or multiples of one, to usefully single step. If you've a 50mhz clock, do 'run ? ns' to get to the interesting bit then 'run 20 ns' 'run 40 ns' etc to step through it. That should give you what you're looking for.





Good luck :)
Click to expand...

I guess this method is a very good idea to debug. Thanks a lot. :)

Abhishek
 

You're welcome and I hope it helps :)
 

During debug you can also use some support as it happens in debugging software: you can either use asserts or you can dump to text file selected signals, and it might be useful for debugging only a portion of the VHDL model semi-automatically.

Cheers
 

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