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[SOLVED] vhdl output cannot be read

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Hi
I am trying a full adder design
I need to check if the carry is 1 or 0

cout: out STD_LOGIC;

process (cout)
begin
if ( cout ='0') then

---
---
--
else
--
---
end if;
end process;

it gives me an error that cout is an output and can't be read
How can I test an output signal??even if I try to define a signal and transfer the value of cout to that signal I get the same error
thnx
 

This is an odd quirk from VHDL that annoys most verilog users.

The solution is to create a signal inside your design, eg "cout_buf" and then assign "cout <= cout_buf;".
there are also ways to use a port type of "buffer", but this has other issues when connecting modules, so it is best just to use the extra signal method.

I suggest _buf as the suffix. _i and _int are also common (for "internal"), but also are common for "input" or "integer". Of course _buf might imply an IO buffer...
 

Old VHDL versions had the problem that a port of the buffer type must be continued as buffer through the hierarchy. The restriction doesn't apply to recent VHDL. But the suggestion to copy the signal is reasonable for clarity, though.
 

I have defined a signal cout_temp
cout_temp <= cout
but I also got the same error,
cout is the output of a schematic full adder that I mapped it in my design

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I have defined a signal cout_temp
cout_temp <= cout
but I also got the same error,
cout is the output of a schematic full adder that I mapped it in my design
 

You would do it the other way around, as permute suggested. cout_temp as internal signal, assigned to the port out signal:
cout <= cout_temp
 
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create a
signal cout_temp : std_logic;

[in process]
cout_temp <= a + b;
[end process]

cout <= cout_temp;

then you can check ur signal at cout_temp :)

expand what "FvM means"
 
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I understand what you are saying, but if this output is taken from an entity that is included in my design as a port map, I cannot add any signal to that entity , I need to test this output in the top level design. this is the problem
 

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