clock gate cloning using SoC encounter

hi,

what is clock cloning?
How it can be implemented using SoC encounter?
Can any one plz help.

I googled this http://www.cdnusers.org/community/encounter/Resources/resources_lp/tp_Teng_edited.pdf page 12~13 gives general description and purpose of this Cadence feature
It is a dynamic power reduction by gating method of distributed clock

If some one could tell the brief flow, that would be more helpful

on what basis a PD engineer will decide whether clock gating must be done or not?

page 12 of PDF slide show a good reason. reduce dynamic power being consumed by clock fannout. Using Gates selects when the clock is needed rather than enable a counter or register.... So its to conserve power.

Hi pavi622,
Clonning:-let us assume that a cell is driving a fanout of sixty than the output load across output pin of cell will increase this will lead to high dyanamic power disppiation and input tran violation of next cell that is being driven by output load of this cell.So,for that reason we divide the sixty fanout into two parts(thirty,thirty) by keeping two drive strength bufffers such that the power dissipiation will decrease this method is called clonning....,Hope this can help you...,correct me if i am wrong....,

---------- Post added at 09:36 ---------- Previous post was at 09:27 ----------

Hi pavi622..,

simply we can say this also as clonning
Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy

thank you,
i have some more doubts,
1. what is the difference between prePD and postPD netlist?
2. how does total power & power density differ wrt PD?