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Sending loop for long signals in VHDL

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timsanr

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HI,
when I have FSM, I can send via UART 1 byte in one state and then go to the next. But if I'd like to send data signal containg e.g 40 bits, how can I do it in some loop, instead of creating 5 states (one for sending signal(39 downto 32), next for signal(31 downto 24), ...) ? I can some counter from 5 to 0 but how to load appropriate part of signal to 8 bits uart_send signal?
 
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the state machine is most appropriate, or wait till the counter counts down to 0, or up to 5 (depending on which way you want to count).

VHDL loops are not appropriate here.
 
OK, but if I will have 512 bits to send, better for me is to not create 64 states :) How to change signal range to next 8 bit every counter increment/decrement? Could you write some example template? I'm not adept in VHDL and now can't figure it out.
 

the input data bus should always be fixed, so you just need to count however many you want to send.
for example - the input data bus is 8 bits, but you want to send 100 bytes, you just count to 100.
 

So every count I need to change data byte like:
Code: 
to_fifo <= data_signal(range2 downto range1);

What is the best way to change range1, range2 values? Now I use variables and change their values by 8.
 

you could do that, but how big is your data_signal? it cannot change it size on the during runtime.
 

Actually I have three types of data: 48, 136 and 512 bits and don't change size during runtime. Depend which type I want to send I change byte_counter. It works now but I have another problem. I used FIFO and UART modules from Pong P. Chu "FPGA Prototyping by VHDL Examples" book. It worked good but FIFO took almost all resources on Spartan3 when has 256 bytes size. I changed it to FIFO from Core Generator (believe it's the best implementation) but now it always sends 0 as first byte. UART starts to transmit when negated 'empty' signal from FIFO is true so FIFO should has contents then, but it seems read pointer is to high by one. Do you have idea why it is like this?
 

Its probably telling there is data, but is not in "look ahead" mode. In look ahead mode, the empty works as a "data valid", and the next data arrives when you assert rd_en.
For normal mode, the empty flag says there is data, and data arrives 1 clock after you assert read_en.
 
That was very helpful information. It must be this feature in Core Generator:
"The first-word fall-through (FWFT) feature provides the ability to look-ahead to the next word
available from the FIFO without issuing a read operation. When data is available in the FIFO, the first
word falls through the FIFO and appears automatically on the output bus (DOUT)."
I have always chosen Standard mode. I will test it tomorrow. Thanks a lot.
 

be aware, that look ahead or fall through mode will have a slower FMax
 

Good to know. FIFO works as I wanted, I receive correct data in terminal :) In this moment I have to focus on appriopriate operations. Later I will have to think about fast data transfer to outside world. BTW do you have any idea how to transfer data to PC faster than by USB. Is it possible to use Ethernet? I should then implement all the stack?
 

Xilinx should provide an ethernet core, otherwise you may have to get it from a 3rd party. There may be a cost involved, but at least you wont have to implement it yourself (as its rather complicated)
 
timsanr said:
Is it possible to use Ethernet? I should then implement all the stack?
Click to expand...
If you use UDP (packets, not a stream) and static ARP (IP address to MAC address mapping) in the other end, you don't need a stack at all.
 
I think I should be intrested in this because I have to achieve 50MB/s. Hope it is possible.

EDIT:
So I have problem unfortunately.
With this:
Code: 
to_fifo <= data_signal(range2 downto range1);
When data_signal has 48 bits size, synthesis last short. But when I try to assign 144 bits signal which is a part of 146 bits signal (without first and last bit), it is synthesized very long. It stood long when tried to make FSM with sending and I see that used resources list is much longer than other, more complicated FSMs in my project :
Code: 
 Summary:
	inferred   1 Finite State Machine(s).
	inferred   4 Counter(s).
	inferred 607 D-type flip-flop(s).
	inferred   7 Adder/Subtractor(s).
	inferred   1 Comparator(s).
	inferred  56 Multiplexer(s).
	inferred   2 Tristate(s).

Later it was also slow. All took almost 30 minutes. Is it possible to improve it?
 
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I need to bump this thread because still don't have idea how to work with long signals.
 

why not post some code that you've done already. It might give us more of a clue.
 

Sorry. All the FSM is a bit expanded now and I didn't wanted to cut negligible parts, I though it will be enough if I describe issue. I deal with it using array with 8 bits signals, I divided that long signal.
 

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