madalin1990
Full Member level 2
I am trying to decribe a verilog module for a multiplexed display,but i just keep doing it wrong.Here is what i have tried.If someone could tell me where is my mistake i would be grateful.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 module selector( clk, rst, an_sel, data0, data1, data2, data3, data4, data_out ); input clk,rst; output reg [4:0] an_sel; output reg [2:0] data_out; input [7:0] data0,data1,data2,data3,data4; reg q; always @(posedge clk,posedge rst) begin:COUNTER if(rst == 1'b1)begin q <=3'b0; end else if(q==3'b100)begin q<= 3'b0; end else begin q<=q+1; end end reg sel; always @(q) begin if(q==3'b0)begin an_sel <=5'b00001;// 5'b10000; sel<=3'b0; end else if(q==3'b001)begin an_sel <= 5'b00010;//5'b01000; sel<=3'b001; end else if(q==3'b010)begin an_sel <=5'b00100;// 5'b00100; sel<=3'b010; end else if(q==3'b011)begin an_sel <=5'b01000;//5'b00010; sel<=3'b011; end else begin an_sel <=5'b10000;// 5'b00001; sel<=3'b100; end end always @(sel) begin case(sel) 0:data_out = data0; 1:data_out = data1; 2:data_out = data2; 3:data_out = data3; 4:data_out = data4; default : data_out=~8'b00111111; endcase end endmodule
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